本研究旨於探討積體電路封裝的失效模式與設計規範準則，透過有限元素模擬模的方式來進行分析，首先針對覆晶與打線封裝技術上的條狀翹曲失效模式，釐清不同製程參數、結構設計與材料種類對於條狀翹曲的影響，本研究所開發的條狀翹曲模型與實驗值誤差值僅在13.7%以下，而過去文獻誤差都高達20%以上，並探討不同製程參數(封膠、固化烘烤與錫球植入迴焊等)、結構設計與材料種類對於條狀翹曲的影響，進行田口與最佳化分析，找出主要關鍵因子為晶粒、模製化合物以及基板厚度，次要因子為封膠溫度。提出兩種設計準則與規範，第一種提高晶片結構厚度與降低封膠溫度，藉由最佳化參數設計，使得覆晶與打線條狀翹曲降低68.30%與97.89%。但提高結構厚度不符合產品輕薄化，第二種設計準則與規範，搭配中性軸公式，採用較小的條狀中性軸(zn)與晶粒形心(zdie)間距離比率(覆晶從0.03%調整到-9.80%；打線從-1.25%調整到-10.92%)，覆晶與打線製程的條狀翹曲可降低25.54%與32%，不只降低條狀翹曲，亦可減少模製化合物的成本44.44%與19.77%。第二部分，針對晶圓級封裝晶片失效模式部分，本研究成功建立晶圓級封裝晶片壽命評估模型，估算出封裝體在進行溫度循環測試時的疲勞壽命，模型估算之晶片壽命與實驗值的誤差值僅有4.6%，相較過去文獻10% 大幅改善。不僅如此，本研究更針對模製化合物不同包覆設計與厚度，分別深入探討對於晶片壽命之影響。將模製化合物厚度從產線85 µm改為25 µm，可以使晶片壽命從652次提高到1230次，超過產線需求標準500次，壽命提升為1.86倍，模製化合物使用量降為29%。綜合上述，本研究開發之條狀翹曲與晶片壽命評估模型提出的設計規範可望應用在積體電路封裝設計上，以提升產品良率與降低生產成本。

This study aimed to investigate a failure mode for integrated circuit package and design specification. This study successfully established a design rule for flip-chip and wire-bonding package, and the error of strip warpage models is within 13.7%. In order to reduce strip warpage, the die thickness and compound thickness must be increased while and the molding temperature must be decreased. But this design does not meet the needs of light, thin, short and small production lines. To solve this problem, the structural design criteria proposed in this study use a smaller ratio of the neutral axis of the strip (zn) to the dice centroid (zdie). Results show that this strategy can reduce warpage and overall thickness of the strip effectively. Besides, an evaluation model of chip fatigue life during a temperature cycle test for WLP (wafer level package) technology is also discussed in this work. The simulation results differed from the experiment results by only 6.4%. Additionally, the effects of molding compound protection type and thickness on fatigue life are investigated. When the thickness is changed from 85 to 25 µm, the fatigue life increased to approximately 1230 cycles, which is up to 1.86 times. Reduction in molding compound thickness reduced the amount of material required to 29% in the production line. The proposed design specifications are expected to be applied to the design of integrated circuit package, and thus meet the requirement of thin and compact production lines, accelerate product development cycles, improve product quality, and reduce development costs.

論文審定書 i
誌謝 ii
中文摘要 iii
Abstract iv
目錄 v
圖次 viii
表次 xii
符號說明 xv
1. 導論 1
1.1 前言 1
1.2 積體電路封裝失效問題之現況探討 3
1.2.1條狀翹曲失效模式 3
1.2.2晶圓級封裝晶片失效模式 6
1.3 研究動機與目標 8
1.4 論文架構 10
2. 積體電路封裝模型建立 11
2.1覆晶條狀翹曲模型 11
2.1.1 覆晶晶片封裝製程流程 11
2.1.2 翹曲模型建立 13
2.2 打線條狀翹曲模擬模型 30
2.2.1 打線晶片封裝製程流程 30
2.2.2 翹曲模型建立 31
2.3晶圓級封裝晶片壽命評估模型建立 43
2.3.1 晶圓級封裝晶片製程流程 43
2.3.2 壽命評估模型建立 44
2.3.3 晶片壽命評估公式 51
3. 積體電路封裝模型驗證與設計 60
3.1 覆晶與打線條狀翹曲模型驗證 60
3.1.1覆晶條狀翹曲模型驗證 60
3.1.2打線條狀翹曲模型驗證 61
3.2 覆晶與打線條狀翹曲田口設計 63
3.2.1覆晶條狀翹曲模型田口設計 65
3.2.2打線條狀翹曲模型田口設計 69
3.3 晶圓級封裝晶片壽命評估模型驗證 73
4. 結果與討論 77
4.1最佳化分析 77
4.1.1 覆晶條狀翹曲晶片田口分析與最佳化設計 77
4.1.2 打線條狀翹曲晶片田口分析與最佳化設計 88
4.1.3 晶圓級封裝晶片 100
4.2設計準則與規範 106
4.2.1 覆晶晶片之中性軸計算 106
4.2.2 打線晶片之中性軸計算 112
4.2.3 晶圓級封裝晶片壽命 119
4.3新穎性分析 120
5. 結論與未來展望 123
5.1 結論 123
5.2 未來展望 125
參考文獻 126
附錄 132
A.條狀基板模擬模型設定流程 132
物理量選擇與研究選擇 132
幾何結構建立 137
材料參數設定 146
邊界條件設定 163
模型網格化設定 178
研究求解器設定 180
B.晶圓級封裝晶片模擬模型設定流程 183
物理量選擇與研究選擇 183
幾何結構建立 187
材料參數設定 188
邊界條件設定 194
模型網格化設定 196
研究求解器設定 197

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