近年來，由於邊緣運算(Edge Computation) 的快速發展，需要大量的運算能力及記憶體，同時帶來了低功耗需求。其中電源管理積體電路(Power Management Integrated Circuit, PMIC) 中包含了許多子電路，如直流/直流轉換器(DC/DC Converter)與低壓降穩壓器(Low-dropout Regulator, LDO)，為了因應LPDDR5 I/O 要求的工作電壓，同時達到推動極大負載之需求，本論文提出兩個設計，分別為具負電壓單電感雙輸出降壓-降壓轉換器，該架構同時輸出VDDQ (0.5 V/0.3 V) 電壓給IO，以及負電壓VNeg (-0.4 V/-0.6 V) 作為推動PMOS 閘極的低電壓準位，與具增加迴轉率電路與增強回收尾電流浮動AB 類雙級運算放大器，作為LDO 所需之高迴轉率功率放大器。
　　本論文第一個研究題目為具負電壓單電感雙輸出降壓-降壓轉換器，使用TSMC 40 nm CMOS 製程實現，同時輸出VDDQ (0.5 V/0.3 V) 電壓給IO，以及負電壓VNeg (-0.4 V/-0.6 V) 作為推動PMOS 閘極的低電壓準位，根據後模擬結果，輸出電壓為0.5 V/-0.4 V 時，VO1 端負載調整率為0.083 mV/mA，交叉調整率為0.078 mV/mA，VO2 端負載調整率為0.064 mV/mA，交叉調整率為0.026 mV/mA，輸出電壓為0.3 V/-0.6 V 時，VO1 端負載調整率為0.025 mV/mA，交叉調整率為0.158 mV/mA，VO2 端負載調整率為0.029 mV/mA，交叉調整率為0.022 mV/mA。
　　本論文第二個研究題目為具增加迴轉率電路與增強回收尾電流之浮動AB 類雙級運算放大器，使用UMC 0.18 μm CMOS 1P6M 製程實現，本設計提出一個浮動AB 類運算放大器，藉由增強回收尾電流源偵測差動輸入值僅在偵測到瞬間大訊號變化時提升偏壓電流，在不犧牲功率消耗下增加迴轉率，並使用新型增加迴轉率電路進一步提升輸出擺幅、迴轉率與正負迴轉率對稱性，最差角落後模擬結果，正迴轉率為65.6 V/μs，負迴轉率為129 V/μs，平均迴轉率為97.3 V/μs，正負迴轉率差異縮小66.88 %，且安定時間為67.3 ns，量測結果正迴轉率為47.21V/μs，負迴轉率為115.55 V/μs，平均迴轉率為81.38 V/μs，安定時間為75.6 ns。

　　Recently, the fast growth of Edge Computing brings the necessary of significant computing power, memory, and low power consumption. Power Management Integrated Circuits (PMICs), which include various sub-circuits such as DC/DC converters and Low dropout Regulators (LDOs), must meet the I/O voltage requirements of LPDDR5 and support large load demands. This thesis presents two designs: a Single Inductor Dual Output Buck-Buck Converter that generates a positive voltage of VDDQ (0.5 V/0.3 V) for I/O and a negative voltage of VNeg (-0.4 V/-0.6 V) for driving PMOS gates, and a Free Class AB two-stage operational amplifier with boosted recycling tail current recovery, designed to serve as a high slew rate power amplifier for the LDO.
　　The first research topic focuses on the Single Inductor Dual Output Buck-Buck Converter, implemented using TSMC 40 nm CMOS process. It provides VDDQ (0.5 V/0.3 V)for I/O and VNeg (-0.4 V/-0.6 V) for the PMOS gate drive. Post-simulation results indicatea load regulation of 0.083 mV/mA and a cross regulation of 0.078 mV/mA at VO1 (0.5V/-0.4 V) and a load regulation of 0.064 mV/mA and a cross regulation of 0.026 mV/mA at VO2. At 0.3 V/-0.6 V, the load regulation is 0.025 mV/mA and cross regulation is 0.158 mV/mA for VO1 and load regulation is 0.029 mV/mA and cross regulation is 0.022 mV/ mA for VO2.
　　The second research topic presents a Free Class AB Two-Stage OPA, realized usingUMC 0.18 μm CMOS 1P6M process. This design enhances the tail current by increasing bias only during significant input signal changes, thereby improving the slew rate without raising the power consumption. A novel circuit also enhances the balance of the positiveand negative slew rate symmetry. Post-simulation results show the positive slew rate is 65.6 V/μs, the negative slew rate is 129 V/μs, and the average slew rate reaches 97.3 V/μswith 66.88 % reduction of the difference between positive and negative SR and settling time of 67.3 ns.The measured results show positive slew rate is 47.21 V/μs, negative slew rate is 115.55 V/μs, an average slew rate is 81.38 V/μs, settling time is 75.6 ns.

論文審定書. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Thesis Validation Letter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
誌謝. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
論文摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
圖目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
表目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
1 研究背景與動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 前言. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 文獻探討與相關電路. . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 單電感雙輸出直流/直流轉換器架構簡介. . . . . . . . . . . . 4
1.2.2 高迴轉率運算放大器架構簡介. . . . . . . . . . . . . . . . . . 9
1.3 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.1 具負電壓單電感雙輸出降壓-降壓轉換器. . . . . . . . . . . . 13
1.3.2 具增強回收尾電流浮動AB 類雙級運算放大器. . . . . . . . . 14
1.4 論文大綱. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 具負電壓單電感雙輸出降壓-降壓轉換器. . . . . . . . . . . . . . . . . . . . 16
2.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 單電感雙輸出電壓轉換器控制方法. . . . . . . . . . . . . . . . . . . 16
2.3 系統架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4 電路設計與分析. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4.1 開迴路單電感雙輸出降壓-降壓轉換器. . . . . . . . . . . . . 19
2.4.2 具負電壓單電感雙輸出型態責任週期公式推導. . . . . . . . 20
2.4.3 電感電流與控制訊號波形. . . . . . . . . . . . . . . . . . . . 23
2.4.4 次臨界區運算放大器. . . . . . . . . . . . . . . . . . . . . . . 26
2.4.5 電流感測器. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5 電路模擬與預計規格. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5.1 晶片佈局. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5.2 具負電壓單電感雙輸出降壓-降壓轉換器佈局後模擬結果. . . 29
2.6 晶片量測結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6.1 量測環境. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6.2 量測結果與分析. . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.7 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3 具增加迴轉率電路與回收尾電流浮動AB 雙級運算放大器. . . . . . . . . 47
3.1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2 系統架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3 電路設計與分析. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.1 增強回收尾電流. . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.2 β 乘法型參考電壓源. . . . . . . . . . . . . . . . . . . . . . . 49
3.3.3 靜態回收尾電流直流分析. . . . . . . . . . . . . . . . . . . . 50
3.3.4 回收尾電流正差動輸入訊號分析. . . . . . . . . . . . . . . . 51
3.3.5 迴轉率增加電路. . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4 模擬結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.4.1 晶片佈局. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.4.2 具增加迴轉率電路與回收尾電流浮動AB 類雙級運算放大器
後模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.5 晶片量測結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.5.1 量測環境. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.5.2 量測結果與分析. . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.6 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4 結論與未來研究方向. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.1 研究成果與結論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.2 未來研究規劃. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
附錄一：單電感雙輸出降壓-降壓轉換器佈局後模擬. . . . . . . . . . . . . . . 77
附錄二：浮動AB 類雙級運算放大器轉態點佈局後模擬. . . . . . . . . . . . . 80
參考文獻. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

[1] J. Hwang, L. Nkenyereye, N. Sung, J. Kim and J. Song, “IoT service slicing and task offloading for edge computing,” IEEE Internet of Things Journal, vol. 8, no. 14, pp.11526-11547, Jul. 2021.
[2] L. Nkenyereye, J. Hwang, Q. -V. Pham and J. Song, “Virtual IoT service slice functions for multiaccess edge computing platform,” IEEE Internet of Things Journal, vol.8, no. 14, pp. 11233-11248, Jul. 2021.
[3] M. AlSelek, J. M. Alcaraz-Calero and Q. Wang, “Dynamic AI-IoT: enabling updatable AI models in ultralow power 5G IoT devices,” IEEE Internet of Things Journal, vol.11, no. 8, pp. 14192-14205, Apr. 2024.
[4] G. Bedi, G. K. Venayagamoorthy, R. Singh, R. R. Brooks and K. -C. Wang, “Review of Internet of Things (IoT) in electric power and energy systems,” IEEE Internet of Things Journal, vol. 5, no. 2, pp. 847-870, Apr. 2018.
[5] Y. Liu, M. Peng, G. Shou, Y. Chen and S. Chen, “Toward edge intelligence: multiaccess edge computing for 5G and Internet of Things,” IEEE Internet of Things Journal, vol. 7, no. 8, pp. 6722-6747, Aug. 2020.
[6] M. Agiwal, A. Roy and N. Saxena, “Next generation 5G wireless networks: a comprehensive survey,” IEEE Communications Surveys & Tutorials, vol. 18, no. 3, pp. 1617-1655, Dec. 2016.
[7] M. R. Palattella et al., “Internet of Things in the 5G era: enablers, architecture, and business models,” IEEE Journal on Selected Areas in Communications, vol. 34, no. 3, pp. 510-527, Mar. 2016.
[8] Y. Liu, Z. Qin, M. Elkashlan, Z. Ding, A. Nallanathan and L. Hanzo, “Nonorthogonal multiple access for 5G and beyond,” Proceedings of the IEEE, vol. 105, no. 12, pp. 2347-2381, Dec. 2017.
[9] F. Al-Doghman, N. Moustafa, I. Khalil, N. Sohrabi, Z. Tari and A. Y. Zomaya, “AI enabled secure microservices in edge computing: opportunities and challenges,” IEEE Transactions on Services Computing, vol. 16, no. 2, pp. 1485-1504, Mar. 2023.
[10] S. Deng, H. Zhao, W. Fang, J. Yin, S. Dustdar and A. Y. Zomaya, “Edge intelligence: the confluence of edge computing and artificial intelligence,” IEEE Internet of Things Journal, vol. 7, no. 8, pp. 7457-7469, Aug. 2020.
[11] J.-S. Kim et al., “A 512 Mb two-channel mobile DRAM (oneDRAM) with shared memory array,” IEEE Journal of Solid-State Circuits, vol. 43, no. 11, pp. 2381-2389, Nov. 2008.
[12] W. Choi, T. Kim, J. Shim, H. Kim, G. Han and Y. Chae, “23.8 A 1V 7.8mW 15.6Gb/ s C-PHY transceiver using tri-level signaling for post-LPDDR4,” 2017 IEEE International Solid-State Circuits Conference (ISSCC), pp. 402-403, Feb. 2017.
[13] M. H. Hajkazemi, M. K. Tavana and H. Homayoun, “Wide I/O or LPDDR3 exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies in embedded MPSoCs,” 2015 33rd IEEE International Conference on Computer Design (ICCD), pp. 62-69, Oct. 2015.
[14] Richtek Technology Corporation, “Portable devices,” Richtek Technology Corporation. Available:https://www.richtek.com/Home/applications/consumer-electronics/portable-devices?ForceDevice=1&devicename=richtekweb&sc_lang=en
[15] Hung Vuong, Jedec memory for automotive LPDDRx & UFS, Qualcomm Tech, Inc.,2023.Available:https://www.jedec.org/sites/default/files/FINAL_Hung_Vuong
_Automotive_forum-memory%20technologies.pdf
[16] K.-S. Ha et al., “23.1 A 7.5Gb/s/pin LPDDR5 SDRAM with WCK clocking and nontarget ODT for high speed and with DVFS, internal data copy, and deep-sleep mode for low power,” IEEE International Solid-State Circuits Conference, pp. 378-3801,
Feb. 2019.
[17] K.-S. Ha et al., “25.2 A 16Gb sub-1V 7.14Gb/s/pin LPDDR5 SDRAM applying a mosaic architecture with a short-feedback 1-tap DFE, an FSS bus with low-level swing and an adaptively controlled body biasing in a 3rd-generation 10nm DRAM,”
2021 IEEE International Solid-State Circuits Conference (ISSCC), pp. 346-348, Feb.2021.
[18] S. Gupta, “3-T (8-T) decoupling capacitors for Improved PDN in LPDDR4/4X/5 system” 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), pp. 2097-2102, May 2019.
[19] K.-S. Ha et al., “A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM with various high speed and low power techniques,” IEEE Journal of Solid-State Circuits, vol. 55, no. 1, pp. 157-166, Jan. 2020.
[20] C. Shi, B. C. Walker, E. Zeisel, B. Hu and G. H. McAllister, “A highly integrated power management IC for advanced mobile applications,” IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp. 1723-1731, Aug. 2007.
[21] S. M. Anisheh, H. Abbasizadeh, H. Shamsi, C. Dadkhah and K. -Y. Lee, “98-dB gain class-AB OTA with 100 pF load capacitor in 180-nm digital CMOS process,” IEEE Access, vol. 7, pp. 17772-17779, May 2019.
[22] S. Sutula, M. Dei, L. Terés and F. Serra-Graells, “Variable mirror amplifier: a new family of process-independent class-AB single-stage OTAs for low-power SC circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers,vol. 63, no. 8, pp. 1101-1110, Aug. 2016.
[23] E. N. Y. Ho and P. K. T. Mok, “A capacitor less CMOS active feedback low dropout regulator with slew rate enhancement for portable on chip application,” IEEE Transactions on Circuits and Systems II: Express Briefs,vol. 57, no. 2, pp. 80-84, Feb. 2010.
[24] J. Tang, J. Lee and J. Roh, “Low power fast transient capacitor-less LDO regulator with high slew rate Class AB amplifier,” IEEE Transactions on Circuits and Systems II: Express Briefs,vol. 66, no. 3, pp. 462-466, Mar. 2019.
[25] K.-C. Wu, H.-H. Wu and C.-L. Wei, “Analysis and design of mixed-mode operation for noninverting buck–boost DC–DC converters,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 12, pp. 1194-1198, Dec. 2015.
[26] H.-W. Chang, W.-H. Chang and C.-H. Tsai, “Integrated single-inductor buck-boost or boost-boost DC-DC converter with power-distributive control,” 2009 International Conference on Power Electronics and Drive Systems (PEDS), pp. 1184-1187, Nov.
2009.
[27] K. I. Hwu, Y. T. Yau and J.-J. Shieh, “Dual-output buck-boost converter with positive and negative output voltages under single positive voltage source fed,” The 2010 International Power Electronics Conference - ECCE ASIA, pp. 420-423, Jun. 2010.
[28] Anna Sunny, Neena Mani, Dinto Mathew and Beena M. Varghese, “A negative dual output DC-DC converter with dual working modes,” Materials Today: Proceedings, vol. 58, Part 1, pp. 552-561, Mar. 2022.
[29] R. S. Assaad and J. Silva-Martinez, “The recycling folded cascode: a general enhancement of the folded cascode amplifier,＂IEEE Journal of Solid-State Circuits, vol. 44, no. 9, pp. 2535-2542, Sept. 2009.
[30] Y. Xin, X. Zhao, B. Wen, L. Dong and X. Lv, “A high current efficiency two-stage amplifier with inner feedforward path compensation technique,＂IEEE Access, vol. 8, pp. 22664-22671, Dec. 2020.
[31] J. Ramirez-Angulo, R. G. Carvajal, J. A. Galan and A. Lopez-Martin, “A free but efficient low-voltage class-AB two-stage operational amplifier,＂IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 7, pp. 568-571, Jul. 2006.
[32] A. Salimath et al., “An 86% efficiency SIMO DC-DC converter with one boost, one buck, and a floating output voltage for car-radio,＂2018 IEEE International Solid - State Circuits Conference (ISSCC), pp. 426-428, Feb. 2018.
[33] S.-P. Lin and M.-D. Ker, “Design of stage-selective negative voltage generator to improve on-chip power conversion efficiency for neuron stimulation„＂IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp. 4122-4131,Nov. 2020.
[34] V. Khasiev, Produce negative voltages using the Buck controller, Analog Device, Inc., 2020. Available: https://www.analog.com/en/resources/design-notes/producenegative-voltages-using-the-buck-controller.html.
[35] M. Zhu and F. L. Luo, “Implementing of developed voltage lift technique on SEPIC, cûk and double-output DC-DC converters,” 2007 2nd IEEE Conference on Industrial Electronics and Applications, pp. 674-681, May 2007.
[36] J. Li and J. Liu, “A negative-output high quadratic conversion ratio DC–DC converter with dual working modes,” IEEE Transactions on Power Electronics, vol. 34, no. 6, pp. 5563-5578, Jun. 2019.
[37] P. Klimczak and P. Munk-Nielsen, “A single switch dual output nonisolated boost converter,＂2008 Twenty-Third Annual IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 43-47, Feb. 2008.
[38] F. A. Himmelstoss and W. Kraeftner, “Analysis of a device for converting a unipolar input voltage into two symmetric bidirectional output voltages with a magnetically coupled coil,＂2008 13th International Power Electronics and Motion Control Conference
(PEMC), pp. 331-336, Feb. 2008.
[39] F. Mao et al., “A power efficient hybrid single-inductor bipolar-output DC-DC converter with floating negative output for AMOLED displays,” 2020 IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, Mar. 2020.
[40] M. Rashtian, “Slew rate enhancement using recycling tail current source,＂Iran J Sci Technol Trans Electr Eng 48, pp.523–532, Jan. 2024.
[41] J. Beloso-Legarra, C. A. De La Cruz-Blas and A. J. Lopez-Martin, “Power efficient single stage classAB OTA based on nonlinear nested current mirrors,＂IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 4, pp. 1566-1579, Apr. 2023.
[42] J. Beloso-Legarra, C. A. d. l. Cruz-Blas, A. J. Lopez-Martin and J. Ramirez-Angulo, “Gain-boosted super class AB OTAs based on nested local feedback,＂IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 9, pp. 3562-3573, Sept. 2021.
[43] Y. Wang, Q. Zhang, S. S. Yu, X. Zhao, H. Trinh and P. Shi, “A robust local positive feedback based performance enhancement strategy for non-recycling folded cascode OTA,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 9,
pp. 2897-2908, Sept. 2020.
[44] W.-H. Chang, J.-H. Wang and C.-H. Tsai, “A peak current controlled single inductor dual output DC-DC buck converter with a time multiplexing scheme,” Proceedings of 2010 International Symposium on VLSI Designn, Automation and Test, pp. 331-334, Apr. 2010.
[45] M. Yang, W. Sun, S. Xu, S. Lu and L. Shi, “A 65nm 10MHz single-inductor dualoutput switching buck converter with time-multiplexing control,” 2011 9th IEEE International Conference on ASIC, pp. 870-873, Oct. 2011.
[46] P.-Y. Kuo and S.-D. Tsai, “An enhanced scheme of multi-Stage amplifier With highspeed high-gain blocks and recycling frequency cascode circuitry to Improve gainbandwidth and slew rate,” IEEE Access, vol. 7, pp. 130820-130829, Aug. 2019.
[47] L. Liu, M. Chen, W. Huang, X. Liao and J. Xu, ”A high current efficiency rail to rail Class-AB op amp with dual loop control,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 11, pp. 4218-4222, Nov. 2022.
[48] M. Akbari, S. M. Hussein, Y. Hashim, F. Khateb and K. -T. Tang, ”A rail to rail transconductance amplifier based on current generator circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 10, pp. 1624-1628, Oct.
2023.
[49] T.-J. Lee and D.-Z. Chang, “91.282% efficiency SIDO buck-buck converter with separate positive and negative output voltage in 40 nm CMOS process” 2023 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, May 2023.
[50] W. -T. Yeh, M. -X. Cai, C. -W. Tsai and C. -H. Tsai, “A Single-Inductor Bipolar- Output DC-DC Converter With Tunable Asymmetric Power Distribution Control(APDC) for AMOLED Applications,” IEEE Access, vol. 13, pp. 6810-6819, Mar. 2025.
[51] F. Mao, Y. Lu, F. Maloberti and R. P. Martins, “A Hybrid Single-Inductor BipolarTriple-Output DC–DC Converter With High-Quality Positive Outputs for AMOLED Displays,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no.1, pp. 506-517, Jan. 2023.
[52] Y. Li, M. Huang, R. P. Martins and Y. Lu, “A Single-Inductor Multiple-Output DC– DC Converter With Fixed-Frequency Victim-Last Charge Control for Reduced Cross Regulation” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 8, pp. 3904-3914, Aug. 2024.