本論文提出了一種基於RISC-V架構的神經網路處理器，針對穿戴式裝置和的邊緣運算需求，設計了一種包含神經網路加速器的系統。該系統由兩部分組成：RISC-V處理器和神經網路加速器。其中，神經網路加速器參考Eyeriss架構設計，可以有效降低RISC-V處理器的運算負擔並降低功耗。加速器使用TSMC 40nm製成模擬，並在Zedboard上進行合成模擬。這樣的設計不僅優化了硬件資源的使用，還提高了系統的運算效率和能源效率。
本論文還設計一個基於CNN的EEG分類器，可以有效地進行EEG數據的即時分類。RISC-V處理器主要負責指令轉換和運算，將處理後的指令提供給神經網路加速器，後者則完成數據的分類工作。系統利用CNN模型對EEG數據進行訓練，系統分類準確度可達到97.5%。
此種設計的主要優勢在於系統具有較低的功率消耗，其非常適合應用於能源受限的穿戴式裝置和邊緣運算設備。通過減少對CPU的依賴，此架構可提升了整體系統的運行效率，延長了裝置的續航能力。然而，這種設計也存在一些挑戰，如神經網路加速器的複雜性需要更多的硬體資源和更精細的設計來保證系統的可靠性和效能。未來的工作將集中於進一步優化硬體架構，以及提高系統對不同類型神經網路的支援能力，以增加其應用範圍。

This thesis presents a neural network processor based on the RISC-V architecture, designed for wearable devices and edge computing requirements, featuring a system that includes a neural network accelerator. The system consists of two parts: the RISC-V processor and the neural network accelerator. The accelerator is designed with reference to the Eyeriss architecture, which effectively reduces the computational load on the RISC-V processor and lowers power consumption. The accelerator was simulated using TSMC's 40nm process and synthesized on a Zedboard. This design not only optimizes the use of hardware resources but also enhances the system's computational and energy efficiency.

The thesis also designs a CNN-based EEG classifier that can effectively perform real-time classification of EEG data. The RISC-V processor mainly handles instruction translation and computation, providing processed instructions to the neural network accelerator, which then completes the data classification task. The system uses a CNN model to train EEG data, achieving a classification accuracy of up to 97.5%.

The main advantage of this design is its low power consumption, making it highly suitable for energy-constrained wearable devices and edge computing equipment. By reducing reliance on the CPU, this architecture enhances overall system efficiency and extends device battery life. However, this design also presents challenges, such as the complexity of the neural network accelerator, which requires more hardware resources and more sophisticated design to ensure system reliability and performance. Future work will focus on further optimizing the hardware architecture and improving system support for different types of neural networks to broaden its application range.

論文審定書 i
摘要 ii
Abstract iii
目錄 v
圖次 viii
表次 xi
第1章 緒論 1
1.1 研究動機 1
1.2 論文組織架構 2
第2章 卷積神經網路運算介紹 3
2.1 CNN運算介紹 3
2.1-1 卷積神經網路（CNN） 3
2.1-2 卷積層 (Convolution Layers) 4
2.1-3 激勵函數層（Activation Function Layer） 4
2.1-4 池化層（Pooling Layer） 5
2.1-5 全連接層（Fully Connected Layer） 6
2.2 CNN模型介紹 7
2.2-1 LeNet[2] 7
2.2-2 AlexNet[3] 7
2.2-3 VGG[4] 8
2.2-4 GoogleNet[5][6] 9
2.2-5 MobileNet [7] 10
2.2-6 DenseNet [8] 12
2.2-7 YOLO [9] 13
第3章 研究背景與相關研究 15
3.1 分類器介紹 15
3.1-1 RISC-V CNN協同處理器癲癇檢測應用[10] 15
3.1-2 SVM(Support Vector Machine) 架構癲癇分類器[11] 16
3.1-3 利用無線充電的EEG癲癇分類器[12] 17
3.1-4 具主動學習功能SVM分類器[13] 18
3.1-5 SciCNN處理器[14] 19
3.2 加速器介紹 21
3.2-1 Eyeriss v1[15], Eyeriss v2 [16] 21
3.2-2 Stripes[17] 22
3.2-3 Thinker [18] 22
3.2-4 UNPU [19] 24
3.2-5 Bit Fusion[20] 26
3.3 總結 26
第4章 硬體設計與神經網路模型架構 28
4.1 RISC-V Processor N22 Core[22] 29
4.2 CNN加速器 30
4.2-1 PE 30
4.2-2 Write Back Buffer 32
4.2-3 Output Control 33
4.2-4 Loop Control 33
4.3 CNN模型 33
4.3-1 訓練資料[21] 33
4.3-2 模型架構 34
第5章 硬體與軟體模擬結果 35
5.1 CNN加速器模擬與合成 35
5.2 模擬結果與分析 36
5.2-1 各子集合測試模擬分析 37
5.2-2 軟硬體與整體測試結果比較 48
5.3 合成數據分析 49
5.4 與其他論文比較 53
第6章 結論與未來展望 54
6.1 結論 54
6.2 未來展望 56
參考文獻 56

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