本論文以量測技術為根基發展建立高速及高頻積體電路封裝之電性模型。所研究的封裝種類包括BGA、TSSOP以及BCC等。在BGA封裝的電模型化過程中，頻域及時域量測技術同時被應用並互做比較，發現最佳策略為先用時域技術建立一封裝的粗略耦合傳輸線模型，然後藉由在頻域之最佳化程序將該模型予以修正至最精確的狀態。集總元件模型可藉由傳輸線之分配電路觀念進一步推導而得。
在應用於射頻積體電路封裝上，歸屬於釘架式晶片尺寸封裝形式之一的BCC封裝其電性模型被建立於頻域技術的基礎上。為了驗證模型的準確性及評估封裝的效應，將一條製作於晶片上的50歐姆微帶線予以封裝後並估算及量測其植入與折返損耗，估算與量測值彼此吻合的頻率範圍高達至Ku頻段。封裝所造成的效應為一低通濾波器效應，其頻率響應可由所建立的封裝模型予以成功預估。模擬低通濾波器響應的結果顯示BCC封裝相較於現今常來封裝射頻積體電路之傳統釘架式封裝-TSSOP，有著較高之的截止頻率及較低的通帶植入損耗。

A complete methodology has been proposed to model and evaluate IC packages in the high-speed digital and radio-frequency applications. The package types that are studied in this dissertation include BGAs, TSSOPs and BCCs. In characterization of BGAs, both frequency-domain and time-domain techniques have been applied and compared to each other. It was found that the best strategy was to find a rough coupled transmission-line model in the time domain and refine it through the optimization scheme in the frequency domain. Equivalent lumped model has been further derived from the coupled transmission-line model using the concept of distributed parameters.
For RFIC applications, the electrical model of BCC, one type of lead-frame CSP, has been established based on the frequency-domain technique. To evaluate the package performance, an on-chip 50-ohm microstrip line housed in the package has been investigated. The insertion and return losses were analyzed and measured. Excellent agreement has been observed up to Ku band. The package acts as a low-pass filter to cause a cut off for the line above a certain frequency, which was predicted successfully from the established package model. The simulation results also show that BCC exhibits higher cut-off frequency and lower insertion loss in the passband when compared to TSSOP, one of the currently most popular RFIC packages.

Abstract i
Contents ii
List of Figures iv
List of Tables viii


Chapter 1 Introduction 1
1-1 Ball Grid Array (BGA) Package 1
1-1.1 BGA structure 3
1-1.2 Electrical Characteristics of BGA 4
1-1.3 Future prospect of BGA 6
1-2 Chip Scale Package (CSP) 7
1-2.1 Lead-Frame CSP 7
1-2.2 Manufacturing Process for BCC 8
1-2.3 Electrically and Thermally Enhanced BCC Structures 10
1-3 Package Effects and Characterization 12

Chapter 2 Electrical Modeling of BGA Packages 15
2-1 Measurement Techniques 17
2-1.1 Frequency-Domain Techniques 19
2-1.2 Time-Domain Techniques 22
2-2 Equivalent Transmission-Line and Lumped Models 24
2-3 Summary 28

Chapter 3 Electrical Modeling of RFIC Packages 32
3-1 Modeling for TSSOP 32
3-1.1 Test-Fixture Design and Characterization 33
3-1.2 Coupled-Leads Measurement and Calibration 33
3-1.3 Extraction of the Equivalent Circuit Elements 37
3-1.4 Optimization Schemes for Complete Models 40
3-2 Modeling for BCC++ 44
3-2.1 Measurement Setup 45
3-2.2 Direct Extraction 46
3-3 Summary 50

Chapter 4 Evaluation of RFIC Package Performance 51
4-1 Comparison between 16-pin BCC++ and TSSOP 51
4-1.1 Insertion and Return Losses 52
4-1.2 Monte Carlo Analysis 56
4-2 Evaluation and Verification for BCC++ Models 59
4-3 Summary 66

Chapter 5 Conclusion 67

Appendix A 68

References 70

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