多閘極電晶體已成為最新的趨勢，傳統平面電晶體隨著尺寸持續微縮面臨短通道效應造成各種問題。多閘極電晶體利用立體的結構在源極和汲極之間形成立體線通道，使得元件擁有多面控制閘極的能力，改善閘極的控制力，有效的抑制短通道效應。本實驗利用蝕刻研究 III-V族基板在不同面相的蝕刻特性，利用此特性蝕刻出多閘極電晶體的立體線結構，並將其製作成電容器量測其電性。

Multiple gate devices have become the new trend, traditional bulk devices encounter many problems as the size continuously shrink due to short channel effect. Multiple gate devices have three dimensional wire structure and make devices more sides of gate. This improves the control ability of gate and effectively suppresses short channel effect. In this experiment, we observed different profiles of compound etching. Using the characteristics of etching to form the 3D-wire of multiple gate devices and then measure electronic characteristics of this structure.

致謝 ........................................................................................................ iv
ACKNOWLEDGEMENT ....................................................................... v
摘要 .......................................................................................................... i
ABSTRACT ............................................................................................ii
CONTENTS ...........................................................................................iii
Chapter 1 ................................................................................................. 1
Introduction ............................................................................................. 1
1.1 MOSFET Scaling and Moore’s Law ....................................... 1
1.2 Short-Channel Effects ............................................................. 2
1.3 Multiple Gate MOSFETs ........................................................ 5
1.4 Compound semiconductor and (NH4)2S-treated process .......... 7
1.5 Wet and dry etching ................................................................ 8
1.6 Wet etching solution ............................................................. 11
1.7 Crystallographic etching of compound wafer ........................ 13
Chapter 2 ............................................................................................... 21
Experiments ........................................................................................... 21
2.1 Preparation of compound substrate........................................ 21
2.2 Wet etching of 3D-wire on GaAs and InP substrate .............. 21
2.3 Dry etching of 3D-wire on GaAs and InP substrate ............... 21
2.4 Deposition of silicon dioxide................................................. 21
2.5 Measurements ....................................................................... 22
Chapter 3 ............................................................................................... 24
Results and Discussion .......................................................................... 24
3.1 Profiles of various orientations for GaAs etching .................. 24
3.2 Profiles of various orientations for InP etching ..................... 26
3.3 Dry and wet etching .............................................................. 28
3.4 Characteristics of 3D-wire capacitor ..................................... 29
Chapter 4 ............................................................................................... 49
Conclusion ............................................................................................. 49

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