本篇論文呈現了以類浮動閘極記憶體做為參考電壓產生器和弛緩振盪器組合而成的可調變頻率之時脈產生器並且利用台積電0.35 μm 製程技術實現於晶片上。雖類浮動閘極記憶體的效果不能與標準浮閘記憶體相比，但能以相當低的成本做出相仿的記憶行為。本研究專注於利用類浮動閘極能夠在無須提供電源的情況下儲存資料的特性，使其能夠對振盪器的頻率做調變甚至在切斷電源並在一個小時內重新接回後能保持相同的頻率。因類浮動閘極所產生的參考電壓有範圍限制，故整個時脈產生器提供的頻率範圍介於462 KHz到549 KHz。在類浮動閘極記憶體進行編程的情況下，測得的功耗為5.1 mW並且振盪頻率對電壓源的變化百分比為±1.2%。晶片核心的面積約為0.069 mm2。

This thesis realizes an application-specific integrated circuit (ASIC) implementation of adjustable frequency clock generator which combination of a one-bit quasi floating gate memory as reference voltage generator for the relaxation oscillator with frequency divider at the output stage in TSMC 2P4M 0.35 μm CMOS technology. Quasi floating gate memory can make similar memory behavior with standard cell at a relatively low cost but the effect is compromised. Using the feature which store the data without the power of the quasi floating gate memory, the system can program an oscillator frequency by quasi floating gate memory which keeps the program state even without power but only for an hour. The clock generator can provide oscillating frequency between 462 KHz to 549 KHz. The measured power consumption is 5.1 mW during the quasi floating gate memory operates in program state and the oscillating frequency variation with VDD is about ±1.2%. The chip active area is about 0.069 mm2.

摘要 ii
Abstract iii
Contents iv
List of Figures v
List of Tables ix
Chapter 1 Introduction 1
1.1 Background 1
1.2 Contribution 2
1.3 Thesis organization 2
Chapter 2 System Design 3
2.1 Clock generator specification 3
2.2 System design 4
2.2.1 Quasi floating gate memory operational modes 4
2.3 Relaxation Oscillator working principle 6
2.4 Clock generator 9
Chapter 3 Circuit Design 13
3.1 Reference voltage generator design 13
3.1.1 Floating gate memory 15
3.2 Comparator circuit design 19
3.3 S-R latch circuit design 22
3.4 Delay circuit design 23
3.5 D-type flip-flop frequency divider circuit design 26
3.6 Circuit Layout 28
Chapter 4 Measurement Result 30
4.1 ASIC in D35 technology 30
4.2 Measurement of reference voltage generator 32
4.3 Measurement of frequency divider and clock generator 37
4.4 Comparison 46
Chapter 5 Conclusions and Future Work 48
5.1 Conclusions 48
5.2 Future work 49
References 50
Plagiarism Detection 53

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