本篇論文以90 nm CMOS製程來實現全晶片化的Doherty架構功率放大器設計，在其輸出端是以串聯式變壓器來實現一個功率結合器。期望以Doherty架構來達到強化發射機之平均效率的目的，來解決在退讓功率點上效率低落的問題。本篇論文主要分為兩部分，首先第一個部分針對傳統的線性功率放大器做介紹，並且以晶片來實現一個操作頻率為2.4 GHz的 A類線性功率放大器，其功率電晶體架構採用疊接形式設計；另外在放大器部分採用全差動式設計，因此在輸出端與輸入端採用巴倫器來將訊號做差動與單端的轉換，並且達到阻抗匹配的功能。接著在第二個部分則介紹CMOS Doherty功率放大器設計，並且以晶片來實現一個操作頻率為2.4 GHz的CMOS Doherty功率放大器。本篇論文使用到主要放大器及輔助放大器來做功率結合，為了做到Doherty放大器的操作，主與輔助功率放大器分別設計在AB類以及C類；另外在其輸出端的串聯式變壓器為非對稱式的設計，其目的為提高退讓功率點上的功率轉換效率，進而達到提升發射機之平均效率的目的。

This thesis presents a fully integrated transformer-based Doherty power amplifier in a standard 90 nm CMOS process. Doherty architecture has been proposed to enhancement the average efficiency of the transmitter, and improve efficiency under the back-off. There are two parts of this thesis, the first part is to introduce a traditional linearly power amplifier, and realize a fully integrated class A power amplifier at 2.4 GHz. The cascode structure is used in the power cells since the power amplifier is a fully differential design, a balun is utilized to convert between single-ended and differential signals, and to serve as an impedance matching network. The second part is to realize a fully integrated 2.4 GHz Doherty power amplifier. A main amplifier and an auxiliary amplifier are integrated to have a combined output power. A asymmetrical series combining transformer is used to achieve uneven Doherty operation. The Doherty architecture demonstrates efficiency enhancement under back-off, which is important for high peak-to-average-power-ratio communication systems.

論文審定書 i
誌謝 ii
摘要 iii
Abstract iv
目錄 v
圖目錄 vii
表目錄 x
第一章 緒論 1
1.1 研究背景與動機 1
1.2 章節規劃 8
第二章 CMOS線性功率放大器 9
2.1 線性功率放大器 9
2.1.1 基本設計理論 9
2.1.2 功率放大器設計理論 13
2.1.3 功率放大器分類 18
2.2 晶片電路設計 24
2.2.1 電路架構的選擇與考量 24
2.2.2 設計流程 31
2.2.3 功率放大器設計方法與考量 32
2.2.4 多指狀纏繞式變壓器設計方法與考量 34
2.3 晶片電路模擬與量測結果 38
2.3.1 模擬結果 38
2.3.2 量測方法與儀器設置 40
2.3.3 量測結果討論與檢討 41
第三章 CMOS Doherty功率放大器 47
3.1 Doherty功率放大器 47
3.1.1 Doherty功率放大器理論分析 47
3.1.2 功率結合變壓器理論分析 53
3.2 晶片電路設計 56
3.2.1 架構簡介 56
3.2.2 設計流程 58
3.2.3 放大器設計方法與考量 59
3.2.4 功率結合器設計方法與考量 60
3.2.5 偏壓電路設計方法與考量 62
3.3 晶片電路模擬與量測結果 63
3.3.1 模擬結果 63
3.3.2 量測方法與儀器設置 65
3.3.3 量測結果討論與檢討 66
第四章 結論 67
參考文獻 68

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