中文摘要：
在本論文前半部，主要說明如何利用嵌入技術來精確量測晶片及封裝之寬頻帶散射參數，其間並利用宏捷公司所提供之砷化鎵異質接面雙載子電晶體為式樣，藉由完整之two-step嵌入技術來實際量測異質接面雙載子電晶體之增益頻寬頻率 、最大振盪頻率 ，以驗証分別在使用嵌入技術量測前後之差異。以及利用日月光半導體公司所提供之BCC封裝，以相同嵌入技術量測其散射參數，從而建立其封裝體之電氣模型。而論文後半部，則利用Ansoft公司所發展之高頻模擬軟體HFSS來模擬由中央大學詹益仁教授所提供測試晶片及經BCC封裝後之寬頻帶散射參數，並與量測值做充份比較與討論，以確立模擬技術之準確性。

英文摘要：

In this thesis, a two-step de-embedded techniques was applied to measure the important parameters, ft and fmax , of the heterojunction bipolar transistors(HBTs).
The same technique was also used to measure the wide-band S parameters for modeling and evaluating the bump chip carrier(BCC) packages. In the simulation, the Ansoft HFSS simulator was used to calculate the insertion and return losses for some bare and packaged test chips. Comparison between simulated and measured results has been discussed in detail to illustrate the applicability of the HFSS simulator.

目錄………………………………………………………………………I
圖表目錄……………………………………………………….……………...II
第一章 緒論…………………………………………………………………...1
第二章 晶片及封裝之量測技術……………………………………………...3
2.1 簡介……………………………………………..……………………..3
2.2 高頻元件量測技術……………………………..……………………..3
2.3 量測校正………………………………………..……………………..6
2.4 嵌入校正………………………………………..……………………..8
2.4.1 Two-Step Method……………………………………………….8
2.4.2 Three-Step Method……………………………..……………...10
2.4.3 Four-Step Method…………………………………..………….13
2.4.4 嵌入技術之比較……………………………………...………15
2.5 HBT的 及 量測………………………………………………..16
2.6 BCC的模型化技術………………………………………………….24
第三章 晶片及封裝之模擬技術…………………………………………….28
3.1 BCC 封裝體之介紹…………………………………………………28
3.2 HFSS之模擬技術介紹…………………………………………...…31
3.3 實例驗証……………………………………………………………..33
3.3.1 晶片元件之模擬……………………………………………...33
3.3.2 封裝元件之模擬……………………………………………...50
3.4 模擬之結論…………………………………………………………..65
第四章 結論………..……..………………………………………………….66
參考文獻………………………………………………………...……………67

參考文獻

[1] N. Koshoubu, S. Ishizawa, H. Tsunetsugu, and H. Takahara, “Advanced flip chip bonding techniques using transferred microsolder bumps,” IEEE Transactions on Components and Packaging Technologies, vol. 23, no. 2, pp. 399-403, Jun., 2000.
[2] R. Crowley, “Small, leadless packages moving into production for customer products, ” www.chipscale review.com, Jan.-Feb., 2000.
[3] S. Berry, S. Winkler, “Leadframe CSPs provide an expanding solution to cost objections, ” May-June, 2000.
[4] T.S. Horng, S.M. Wu, H.H. Huang, A. Tseng, and J.J. Lee, “Comparison of advanced measurement and modeling techniques for electrical characterization of BGAs,” Electronic Component and Technology Conference, pp. 1464-1471, 1998.
[5] D. Staculescu, A. Pham, J. Laskar and S. Consolazio, “Analysis and performance of BGA interconnects for RF packaging,” IEEE Radio Frequency Integrated Circuit Symposium, pp. 131-134, 1998.
[6] T. Kawahara, “SuperCSP,” IEEE Transactions on Advanced Packaging, vol. 23, no. 2, pp. 215-219, May, 2000.
[7] J.H. Lau, Flip Chip Technologies, McGraw-Hill, Inc., 1996.
[8] M. Lin, “ASE flip-chip solution,” technical report, R&D Engineering Div., Advanced Semiconductor Engineering, Inc.
[9] A. Magill, “CSP Present and Future,” International Symposium on Advanced Packaging Materials, 1999.
[10] S. C, K. Nguyen, D. Biscan, K. Vu, A. Ferek, and A. Ramos, “Low temperature cofired ceramic (LTCC) for wireless applications” IEEE MTT-S Symposium Digest, pp. 201-205, 1999.
[11] “BCC (Bump Chip Carrier) technology,” technical report, R&D Engineering Div., Advanced Semiconductor Engineering, Inc.
[12] “Bump chip carrier technical brief,” www.fujitsumicro.com, Feb. 1999.
[13] T.S. Horng, S.M. Wu, C. Shih, “Electrical modeling of RFIC packages up to 12 GHz, ”Proc 49th Electronic Components and Technology Conf., pp 867-712, 1999.
[14] T.S. Horng, S.M. Wu, J.Y. Li, C.T. Chiu, and C.P. Hung, “Electrical performance improvements on RFICs using bump chip carrier packages as compared to standard small outline packages,” Proc. 49th Electronic Components and Technology Conf, pp 439-444, 2000.
[15] “Understanding the fundamental principles of vector network analyzers,” Application Note 1287-1, Agilent Technologies.
[16] “Exploring the architectures of network analyzers,” Application Note 1287-2, Agilent Technologies.
[17] “Applying error correction to network analyzer measurements,” Application Note 1287-3, Agilent Technologies.
[18] “Improving throughput in network analyzer applications,” Application Note 1287-5, Agilent Technologies.
[19] 陳棓煌, “向量網路分析儀量測校正方法之研究與實踐,” 中山大學碩士論文, 1996.
[20] 郭明哲, “微帶互連元件電性測試夾具製作與向量網路分析儀量測校正技術之研發,”中山大學碩士論文, 1998.
[21] “In-fixture measurements using vector network analyzers,” Application Note 1287-9, Agilent Technologies.
[22] N. Sahri, T. Nagatsuma, “Packaged photonic probes for an on-wafer broad-band millimeter-wave network analyzer,” IEEE Photonics Technology Letters, vol. 12, pp. 1225-1227, Sept., 2000.
[23] A. Ferrero, U. Pisani, “Two-port network analyzer calibration using an unknown thru,” IEEE Microwave and Guide wave Letters, vol. 2, no.12, pp. 505-507, Dec., 1992.
[24] G. Gronau, I. Wolff, “A simple broad-band devices de-embedding method using an automatic network analyzer with time-domain option,” IEEE Transactions on Microwave Theory and techniques, vol. 37, no. 3, March, 1989.
[25] C.L. Hammond, K.L. Virga, “Network analyzer calibration methods for high-density packaging characterization and validation of simulation models,” Electronic Components and Technology Conference, 2000.
[26] R.B. Marks, “A multiline method of network analyzer calibration,” IEEE Transactions on Microwave Theory and Techniques, vol. 39, no. 7, pp. 1205-1215, July, 1991.
[27] T.E. Kolding, “Impact of test-fixture forward coupling on on-wafer silicon devices measurements,” IEEE Transactions on Microwave and Guided Wave Letters, vol. 10, no. 2, pp. 73-74, Feb., 2000.
[28] N.H. Zha, “Phase uncertainty in calibrating microwave test fixture,” IEEE Transactions on Microwave Theory and Techniques, vol. 47, no. 10, pp. 1917-1922, Oct., 1999.
[29] M.C.A.M. Koolen, J.A.M. Geelen, and M.P.J.G. Versleijen, “An improved de-embedding technique for on-wafer high-frequency characterization,” IEEE. Bipolar Circuits and Technology Meeting, pp. 188-191, 1991.
[30] K.J. Silvonen, “Calibration of test fixtures using at least two standards,” IEEE Transactions on Microwave Theory and Techniques, vol. 39, no. 4, pp. 624-630, April, 1991.
[31] C.H. Kim, C.S. Kim, H.K. Yu, and K. Soo, “An isolated-open pattern to de-embed pad parasitics,” IEEE Microwave and Guided Wave Letters, vol. 8, no. 2, pp. 96-97, Feb., 1998.
[32] H. Cho, D.E. Burk, “A three-step method for the de-embedding of high-frequency S-parameter measurements,” IEEE Transactions on Electron Devices, vol. 38, no. 6, pp. 1371-1375, June, 1991.
[33] S.H. Park, G.H. Lim, and Y.H. Lee, “RF characterization of deep-submicron DRAM-embedded CMOS process,” IEEE. Asia Pacific Conference, pp. 409-412, 1999.
[34] T.E. Kolding, “On-wafer calibration techniques for giga-hertz CMOS measurements,” Microelectronic Test Structures Conference, vol. 12, pp. 105-110, March, 1999.
[35] D. Costa, W.U. Liu, and J.S. Harris, “Direct extraction of the AlGaAs/GaAs heterojunction bipolar transistor small-signal equivalent circuit,” IEEE Transactions on Electron Devives, vol. 38, no. 9, pp. 2018-2024, Sept., 1991.
[36] T.E. Kolding, “A four-step method for de-embedding gigahertz on-wafer CMOS measurements,” IEEE Transactions on Electronic Devices, vol. 47, no. 4, pp. 734-740, April, 2000.
[37] S. Lee, B.R. Ryum, and S.W. Kang, “A new parameter extraction technique for small-signal equivalent circuit of polysilicon emitter bipolar transistors,” IEEE Transactions on Electron Devices, vol. 41, no. 2, pp. 233-238, Feb., 1994.
[38] D.M. Pozar, “Microwave Engineering,” Addison-Wesley Publishing Company, 1990.
[39] S.Lee, “Forward transit time measurement for heterojunction bipolar transistor using simple Z parameter equation,” IEEE Transactions on Electron Devices, vol. 43, pp. 2027-2029, Nov., 1996.
[40] S.Lee, “Effects of pad and interconnection parasitics on forward transit time in HBT’s,” IEEE Transactions on Electron Devices, vol. 46, no. 2, pp. 275-280, Feb., 1999.
[41] T.S. Horng, S.M. Wu, H.H. Huang, C.T. Chiu, and C.P. Hung, “Modeling and evaluating leadframe CSPs for RFICs in wireless applications,” to appear in Electronic Components and Technology Conference, 2001.
[42] T.S. Horng, S.M. Wu, H.H. Huang, C.T. Chiu, and C.P. Hung, “Modeling of lead-frame plastic CSPs for accurate prediction of their low-pass filter effects on RFICs,” to appear in IEEE Radio Frequency Integrated Circuits Symposium, 2001.
[43]吳松茂, “Electrical modeling of IC packages,” 中山大學博士論文, 2001.
[44] “No boundaries-bring together signal integrity and high Frequency design engineers,” Ansoft 2000 HF/SI Workshop.
[45] S.J. Spiegel, A. Madjar, “Impact of light illumination and passivation layer on silicon finite-ground coplanar-waveguide transmission-line properties,” IEEE Transactions on Microwave Theory and Techniques, vol. 48, no. 10, Oct., 2000.
[46] A. Gorur, C.Karpuz, “Effect of finite ground-plane widths on quasistatic parameters of asymmetrical coplanar waveguides,” IEEE Proceedings, Microwave, Antennas and Propagation, vol. 147, no. 5, pp. 343-347, Oct., 2000.