本論文採用升降頻鎖相迴路架構，實現應用於數位電視廣播系統發射端之寬頻頻率合成器。首先對此架構之電路雜訊進行理論分析，了解其對於雜訊壓抑之機制以及最佳化效果，同時利用Matlab及ADS模擬相位雜訊表現。最後佐以不同參考源實現一50 MHz~1 GHz寬頻頻率合成器之混成電路模組，並對相位雜訊表現進行討論。第二部分延伸上述架構發展為以位移鎖相迴路為基礎之寬頻頻率合成器，有別於傳統方式，本論文利用兩電壓控制振盪器之差頻及和頻訊號進行鎖相，來達成寬頻操作目的，並且分析相位雜訊表現，模擬與實作出一300 MHz~3.6 GHz寬頻頻率合成器混成電路模組來加以驗證，然後以CMOS製程設計出此一架構之寬頻頻率合成器。本論文也設計另外兩顆寬頻頻率合成器CMOS晶片，其中壓控振盪器分別使用切換電容與切換電感方式之設計，以達成寬頻操作目的。

The thesis uses an up-down conversion architecture to realize a wideband frequency synthesizer for digital video broadcasting (DVB) transmission system. At first, the theoretical analysis of this architecture is performed to understand the mechanism to suppress the phase noise in an optimal way. Then, the simulations using Matlab and ADS are carried out to predict the phase noise performance. Based on the above efforts, a 50 MHz ~ 1 GHz wideband frequency synthesizer hybrid circuit is implemented and its phase noise performance, corresponding to different choices of the reference sources, is finally discussed. The second part of this thesis is to extend the up-down conversion architecture to an offset phase-locked loop (PLL) architecture for wideband frequency synthesizers. The difference from the conventional offset PLLs is the phase locking of the signal at either the sum or the difference frequency of two voltage-controlled oscillators (VCOs) to the reference source for the purpose of wideband operation. The phase noise analysis of the proposed offset PLL architecture is provided. In the experiments, a 300 MHz ~ 3.6 GHz wideband frequency synthesizer hybrid circuit is implemented to verify the analyzed phase noise results. In addition, a CMOS wideband frequency synthesizer chip using the proposed offset PLL architecture has been realized. Moreover, another two CMOS wideband frequency synthesizer chips are included in this thesis. It is worth mentioning that the VCOs in these two frequency synthesizer chips use the switched capacitor and inductor techniques to achieve a wideband operation.

第一章 緒論 1
1.1 研究背景與動機 1
1.2 寬頻頻率合成器架構簡介 2
1.3 論文章節規劃 4
第二章 運用於DVB系統發射端之寬頻頻率合成器雜訊抑制技術 5
2.1 位移式鎖相迴路架構 5
2.2 相位雜訊抑制理論與分析 6
2.3 相位雜訊模擬 10
2.4 混成電路實現 17
2.4.1 迴路濾波器設計 17
2.4.2 兩階段鎖相切換機制 18
2.4.3 實作量測結果 20
第三章位移式寬頻頻率合成器混成電路與CMOS晶片設計 28
3.1 位移式鎖相迴路架構與雜訊分析 28
3.2 混成電路實現 31
3.2.1 迴路濾波器設計 31
3.2.2實作量測結果 33
3.3 CMOS晶片設計 42
3.3.1 電路架構 42
3.3.2 電路設計與模擬 43
3.3.3 晶片量測結果 47
第四章 切換電容與電感式寬頻頻率合成器CMOS晶片設計 53
4.1 具切換電容陣列之寬頻頻率合成器 53
4.1.1 電路架構 53
4.1.2 電路設計與模擬 53
4.1.3 晶片量測結果 61
4.2 具切換電感與電容陣列之寬頻頻率合成器 65
4.2.1 電路架構 65
4.2.2 電路設計與模擬 66
4.2.3 晶片量測結果 69
第五章 結論 74
參考文獻 76

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