本論文的研究目標是利用平面型變壓器，搭配CMOS與印刷電路板製程技術，設計各種結構之高性能與微型化平衡式被動元件。在CMOS製程下，首先利用三線纏繞變壓器實現具有功率結合與阻抗轉換功\能之並聯結合轉換器，接著為了增加結合埠間之隔離度，使用雙線纏繞變壓器實現威爾金森功率結合器。在FR4及Duroid基板上，運用垂直耦合變壓器結構實現高平衡性巴倫器，接著使用多層基板發展出微型化且具有傳輸零點的巴倫器。最後利用CMOS製程與耦合諧振濾波器理論實現具有通帶設計的變壓器巴倫器，可以限制巴倫器的操作頻寬，藉以改善其在操作頻寬內的CMRR值。

This thesis aims to design transformer-based balanced passive components with high performance and compact size using CMOS and printed-circuit–board (PCB) technologies. A CMOS parallel-combining transformer (PCT) incorporating a planar trifilar transformer is presented to realize power combining and impedance transformation at the same time. In addition, a CMOS Wilkinson power combiner with a planar bifilar transformer is proposed to enhance isolation between two combining ports. Several transformer coupled balun designs with an overlay winding structure are carried out on FR4 and Duroid substrates. These designs uses a rather symmetric layout to achieve a superior balance performance and a multilayer configuration to create the transmission zeros in the out-of-band response. Finally, a CMOS transformer balun is implemented with a bandpass filter passband which is designed according to the coupled resonator filter theory. This passband can restrict the bandwidth usage for the balun to improve the common-mode rejection ratio (CMRR) within the passband.

目錄................................................................................Ⅰ
圖目錄...........................................................................Ⅲ
表目錄...........................................................................Ⅶ
第一章 緒論....................................................................1
1.1 研究背景與動機......................................................1
1.2 章節規劃..................................................................3
第二章 變壓器理論與應用電路介紹............................4
2.1 變壓器基本原理......................................................4
2.2 變壓器結構..............................................................7
2.3 變壓器為基礎之被動元件....................................10
2.3.1 功率結合器(Power Combiner).......................10
2.3.2 巴倫器(Balun)....................................................12
第三章 運用變壓器之功率結合器設計......................14
3.1 並聯結合轉換器....................................................14
3.1.1 CMOS晶片設計.................................................14
3.1.2 模擬與量測結果.................................................19
3.2 威爾金森結合器....................................................23
3.2.1 CMOS晶片設計.................................................23
3.2.2 模擬與量測結果.................................................29
第四章 運用變壓器之巴倫器設計..............................33
4.1 變壓器耦合式巴倫器............................................33
4.1.1 平面與堆疊變壓器耦合式巴倫器架構.............33
4.1.2 Duroid基板元件設計.........................................40
4.1.3 模擬與量測結果.................................................42
4.2 改良之變壓器耦合式巴倫器................................46
4.2.1 Duroid基板元件之微型化設計.........................46
4.2.2 Duroid基板元件之具有傳輸零點設計.............48
4.2.3 模擬與量測結果.................................................49
4.3 具有通帶設計之變壓器耦合式巴倫器.................57
4.3.1 CMOS晶片設計..................................................57
4.3.2 模擬與量測結果..................................................60
第五章 結論...................................................................64
參考文獻........................................................................65

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