本論文主要分為兩部分。第一部分以0.15 μm pHEMT製程設計一AB類功率放大器，利用Volterra series建立可分析記憶效應之非線性模型。在輸入不同頻率間距之連續波雙音訊號時，討論其交互調變項IM3H與IM3L在相位上由於記憶效應所造成的變化。同時提出以數位儲存示波器量測三階交互調變響應的方法，並能與模型分析結果相互驗證。第二部分在研究CMOS功率結合技術，首先比較串聯與並聯結合轉換器架構與優點。接著以0.18 μm CMOS製程設計採用一對並聯結合轉換器做為功率結合用途之E類功率放大器，模擬與實驗結果均顯示其具有高功\\率增加效率。

This thesis consists of two parts. Part one presents a design of class-AB power amplifier in 0.15μm pHEMT process, and establishes a nonlinear model with memory effects for the power amplifier using Volterra series. To observe the memory effects, two-tone continuous wave signals have been applied to the model to predict the phase variation between IM3H and IM3L as a function of tone spacing. In the meanwhile, a time-domain measurement technique for the third-order intermodulation responses using a digital storage oscilloscope has been developed to verify the modeled predictions on IM3H and IM3L. Comparison between modeled and measured results shows good agreement. Part two of this thesis is to study the CMOS power-combining techniques. At first, the pros and cons between series and parallel combining transformers are discussed. Then, a design of class-E power amplifier using a pair of parallel combining transformers for power combining is presented. Both simulated and measured results show that the presented Class-E power amplifier has a high power-added efficiency.

目錄 I
圖表目錄 III
第一章 緒論 1
1.1 背景簡介 1
1.2 章節規劃 3
第二章 功率放大器非線性特性與記憶效應 4
2.1 非線性特性 4
2.1.1 增益壓縮 4
2.1.2 交互調變失真 5
2.1.3 三階交越點 7
2.1.4 多音交互調變比例 8
2.1.5 鄰近通道功率比例 9
2.1.6 Power series理論 9
2.2 記憶效應 13
2.2.1 電熱記憶效應 14
2.2.2 電路記憶效應 16
2.2.3 Volterra series理論 18
第三章 功率放大器非線性模型與電路記憶效應分析 24
3.1 非線性模型 24
3.1.1 AB類功率放大器架構 24
3.1.2 小訊號參數TRL校正量測 26
3.1.3 小訊號等效模型 29
3.1.4 非線性電流源與電容分析 37
3.1.5 Volterra series數學分析 40
3.2 電路記憶效應分析 44
3.2.1 數學模型模擬分析 44
3.2.2 IM3相位量測實驗 49
3.2.3 模擬與量測結果 52
第四章 功率放大器功\\率結合技術研究 59
4.1 串聯與並聯結合轉換器 60
4.2 CMOS功率結合式功\\率放大器設計 65
4.2.1 E類功率放大器架構 66
4.2.2 功率結合架構 69
4.2.3 模擬與量測結果 71
第五章 結論 79
參考文獻 81
附錄A 86
附錄B 88

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