本論文主要為實踐一強化平均效率並具高線性度之無線發射機。本發射機採用波包追隨架構，使用E類功率放大器取代傳統波包追隨架構所使用之線性功率放大器，有效提升發射機之平均效率。且利用FPGA實踐基頻數位電路，產生基頻IQ與波包訊號，可提供精確調制品質與充裕調制頻寬，更有易積體化之優勢。另外針對E類功率放大器之Vdd/AM非線性現象實踐一預失真電路，有效改善發射機線性度，使發射機於不同輸出功率情況下，皆能有兼具高平均效率與高線性度之優異表現。以CDMA2000 1x系統為測試規範，輸入基頻符號率為1.2288 Msps之QPSK調制訊號，使用InGaAs pHEMT製程實踐之E類功率放大器於發射機中，測得平均調制輸出功率於7 ~ 21 dBm範圍內，平均效率為30 ~ 44 %，平均功率增加效率為23 ~ 38 %，ACPR維持44 dBc以上，EVM低於4 %；使用GaAs HBT製程實踐之E類功率放大器於發射機中，測得平均調制輸出功率於4 ~ 18.5 dB範圍內，平均效率為20 ~ 40 %，平均功率增加效率為16 ~ 35 %， ACPR維持43 dBc以上，EVM低於5 %。

This thesis aims to implement a linear wireless transmitter based on the envelope-following architecture. A class-E PA is utilized to replace the linear PA used in the traditional envelope-following transmitter for enhancing the average efficiency. The transmitter relies on a digital processor realized by FPGA to generate the baseband IQ signal and corresponding envelope signal. This way can not only achieve more accurate modulation accuracy and wider modulation bandwidth, but also use less analog components for the future convenience of realizing single-chip integration when compared to the traditional envelope-following transmitter. Furthermore, this thesis implements a predistorter in the digital processor to compensate the Vdd/AM distortion of class-E amplifier. Therefore, this transmitter can simultaneously achieve high efficiency and high linearity over a wide input power range. From the results measured in transmitting a QPSK-modulated CDMA2000 1x signal at a chip rate of 1.2288 Mcps, the transmitter incorporating an InGaAs pHEMT class-E PA can achieve 30~44 % in average efficiency (23~38 % in average PAE) with above 44 dBc in ACPR and below 4 % in EVM in the average modulated output power range from 7 to 21 dBm, while the transmitter incorporating a GaAs HBT can achieve 20~40 % in average efficiency (16~35 % in average PAE) with above 43 dBc in ACPR and below 5 % in EVM in the average modulated output power range from 4 to 18.5 dBm.

第一章 緒論 1
1.1 背景簡介 1
1.2 章節規劃 9
第二章 射頻電路晶片設計 10
2.1 互補切換式直流轉換器架構與設計方法 10
2.1.1 架構簡介 10
2.1.2 設計流程 11
2.2 互補切換式直流轉換器模擬與晶片量測結果 12
2.2.1 模擬結果 12
2.2.2 晶片量測結果 17
2.3 E類功率放大器架構與設計方法 22
2.3.1 架構簡介 22
2.3.2 設計流程 24
2.4 E類功率放大器模擬與晶片量測結果 25
2.4.1 InGaAs pHEMT製程實踐之晶片模擬與量測結果 25
2.4.2 GaAs HBT製程實踐之晶片模擬與量測結果 31
第三章 基頻數位電路設計 36
3.1 基頻數位電路架構簡介 36
3.2 各級電路元件設計 37
3.2.1 IS-95 FIR數位濾波器 37
3.2.2 半頻帶濾波器 38
3.2.3 採用CORDIC演算法之波包產生器 39
3.2.4 線性內插器 42
3.2.5 ㄧ階差異積分調制器 43
3.3 預失真器設計 43
3.3.1 針對pHEMT E類功率放大器設計之預失真器 44
3.3.2 針對HBT E類功率放大器設計之預失真器 49
3.4 數位類比轉換器模組 51
3.5 基頻數位電路輸出訊號量測結果 53
3.5.1 預失真器功能關閉時之基頻IQ訊號量測結果 53
3.5.2 預失真器功能打開時之基頻IQ訊號量測結果 54
第四章 預失真波包追隨發射機整合量測結果 56
4.1 預失真波包追隨發射機整合量測介紹 56
4.2 使用pHEMT E類功率放大器之發射機整合量測結果 57
4.3 使用HBT E類功率放大器之發射機整合量測結果 61
第五章 結論 66
參考文獻 67

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