中文提要：
在採用差異積分調制器之分數式頻率合成器之中，受非線性現象影響而交互調變之量化雜訊可視為污染頻率合成器訊號頻譜純淨度之主要雜訊源。為了探討此非線性現象與研究改善方法，在理論上本論文應用白色量化雜訊理論與非線性分析方法模擬出差異積分調制器在不同階數與架構下量化雜訊之分佈情況，以及使用安捷倫公司所研發的模擬軟體工具ADS來輔助預測頻率合成器之整體相位雜訊表現。實作部分本論文實際完成2.4GHz分數式頻率合成器hybrid模組，在使用不同階數與架構的差異積分調制器，並且考慮變動鎖相迴路頻寬以及參考頻率等條件下量測其相位雜訊。本論文另一個重點是以台積電0.18μm CMOS製程實現2.4GHz鎖相迴路晶片，其供應電壓1.8伏特、消耗電流27mA，操作頻率範圍2120~2380MHz。在迴路頻寬50kHz與參考頻率20MHz下，上下跳頻80MHz時所測得鎖入時間約為40μs，相位雜訊距載波100kHz處約為-90dBc/Hz。

Abstract：
For the fractional-N frequency synthesizers using delta-sigma modulation techniques, the noise source dominant to degrade the spectral purity comes from phase intermodulation of quantization noise due to the PLL nonlinearity. To study and improve the PLL nonlinearity effect, this thesis applies the theory of white quantization noise and nonlinear analysis method to simulate the frequency responses of quantization noises in delta-sigma modulators (DSM) with different order and in various architecture. With the help of Agilent EEsof’s ADS tool, the phase noise performance of the studied fractional-N frequency synthesizers can be well predicted. For demonstration, this thesis work implements a 2.4 GHz fractional-N frequency synthesizer hybrid module, and measures the phase noise under considering various combinations of DSM order and architecture, PLL bandwidth and reference frequency. Another demonstration of this thesis is to implement a PLL IC using 0.18 μm CMOS process. The implemented PLL IC operates in the frequency range from 2120 to 2380 MHz with a supply voltage of 1.8 V and a current consumption of 27 mA. Under the test condition of reference frequency and PLL bandwidth equal to 20 MHz and 50 kHz, respectively, the measured phase noise is 90 dBc/Hz at an offset frequency of 100 kHz and the measured stable time is about 40 μs for a frequency jump of 80MHz.

目錄
目錄 Ⅰ
圖表目錄 Ⅱ
第一章 序論 1
1.1 簡介 1
1.2 章節規劃 2
第二章 頻率合成器之分數式架構非線性效應研究 4
2.1 頻率合成器之非線性現象 4
2.2 高階差異積分調制器架構與設計 6
2.3 差異積分調制器之理論分析與模擬 11
2.4分數式頻率合成器之軟體輔助模擬 18
第三章 2.4 GHz鎖相迴路CMOS晶片設計 24
3.1 相位頻率偵測器 24
3.2 電荷幫浦 27
3.3多模數除頻器 30
3.4 壓控振盪器 34
第四章 2.4 GHz頻率合成器Hybrid模組與鎖相迴路CMOS晶片之實現與量測 38
4.1 分數式頻率合成器模組之實作 38
4.2 分數式頻率合成器模組之測試 45
4.3 鎖相迴路晶片之量測 49
第五章 結論 62
參考文獻 64





圖表目錄
第二章
圖2.1　PFD特性曲線…………………………………………………………5
圖2.2　電荷幫浦 6
圖2.3　一階差異積分調制器 7
圖2.4 MASH 1-1-1架構 8
圖2.5　DSM架構之輸出模數範圍比較 9
圖2.6 單迴路差異積分調制器架構 9
圖2.7　不同截止頻率三階Butterworth之|NTF(z)|比較 10
圖2.8　三階單迴路差異積分調制器(Gmax = 3.1) 11
圖2.9　雜訊轉移函數之絕對值 12
圖2.10　雜訊轉移函數表現之dB值 12
圖2.11　經差異積分調制器雜訊整形後之相位雜訊 14
圖2.12 模數變化 16
圖2.13 除頻器之輸出相位變化 16
圖2.14 非線性分析方法之模型 17
圖2.15　偵測死帶0ps的相位雜訊 17
圖2.16　偵測死帶400ps的相位雜訊 17
圖2.17　分數式頻率合成器模擬環境設定 20
圖2.18　頻率合成器模擬電路 21
圖2.19　利用Lesson's Model逼近實際量測之相位雜訊 22
圖2.20　模擬時引入壓控振盪器雜訊 22
圖2.21 分數式頻率合成器之模擬相位雜訊 23
表2.1 各雜訊轉移函數之整理……………………………………….……….... 12
第三章
圖3.1 傳統式相位頻率偵測器………………………………………..……. 25
圖3.2 修正型預先充電相位頻率偵測器(MPTPFD) 25
圖3.3 PFD輸出波形當兩輸入訊號 26
圖3.4 低頻操作100kHz(相位差180度) 27
圖3.5電流導引式電荷幫浦 28
圖3.6 輸出電流直流特性。 29
圖3.7 電荷幫浦輸出電流不匹配曲線。 29
圖3.8 輸出電流暫態時域表現 29
圖3.9多模數除頻器架構 31
圖3.10第一級之25% duty cycle除2/3電路 31
圖3.11後五級之50% duty cycle除2/3電路 32
圖3.12 控制電路時序圖 32
圖3.13 第一級控制電路 32
圖3.14 高速 ECL to CMOS放大器 33
圖3.15 高速 ECL to CMOS放大器之放大波形 33
圖3.16 多模數除頻器除頻後之輸出波形 34
圖3.17 壓控振盪器之電路圖 35
圖3.18 控制埠電壓對振盪頻率的關係 36
圖3.19 振盪頻率與偏壓電流關係 36
圖3.20 壓控振盪器 37
圖3.21 壓控振盪器之模擬相位雜訊 37
表3.1　200μA電流不匹配指數小於10%之擺幅限制………………………30
第四章
圖4.1 分數式頻率合成器模組之示意圖.……………….……...……... …..38
圖4.2　Peregrine公司之PE3336晶片功能方塊圖. 39
圖4.3 PLL之線性模型 40
圖4.4 主動迴路濾波器 40
圖4.5　系統迴路頻寬100kHz 41
圖4.6　雙點電壓控制振盪器架構圖 42
圖4.7 壓控振盪器之實際電路圖 43
圖4.8　MASH2之輸出模數控制訊號 44
圖4.9 頻率合成器模組之頻譜(參考頻率20MHz) 45
圖4.10　迴路頻寬25kHz之系統穩定時間量測 46
圖4.11　迴路頻寬50kHz之系統穩定時間量測 46
圖4.12　迴路頻寬100kHz之系統穩定時間量測 46
圖4.13　壓控振盪器與整數除頻頻率合成器之相位雜訊比較 47
圖4.14　迴路頻寬25kHz之分數式頻率合成器相位雜訊 48
圖4.15　迴路頻寬50kHz之分數式頻率合成器相位雜訊 48
圖4.16　迴路頻寬100kHz之分數式頻率合成器相位雜訊 48
圖4.17 四階多級雜訊整形在不同參考頻率之相位雜訊 49
圖4.18 鎖相迴路之晶片 50
圖4.19 鎖相迴路之測試板 50
圖4.20 偵測頻率差表現 51
圖4.21　操作頻率20MHz時偵測相位差表現 51
圖4.22 偵測死帶之測量 51
圖4.23　電荷幫浦直流特性之量測示意圖 52
圖4.24　電荷幫浦輸出電流之 53
圖4.25　電荷幫浦暫態時域之量測示意圖 53
圖4.26　操作頻率1MHz時，電荷幫浦之暫態時域表現. 54
圖4.27　操作頻率20MHz時，電荷幫浦之暫態時域表現.. 54
圖4.28 多模數除頻器之量測示意圖 55
圖4.29　操作頻率2.4GHz之除頻後結果 56
圖4.30　壓控振盪器之頻譜表現@2.37GHz 57
圖4.31　調整埠與調制埠之可調頻率範圍(控制電壓0~1.8V) 57
圖4.32 中心頻率2.3795 GHz之壓控振盪器相位雜訊 58
圖4.33　迴路濾波器 59
圖4.34　鎖相迴路量測之示意圖 60
圖4.35　鎖相迴路之輸出訊號頻譜(參考頻率20MHz) 60
圖4.36　鎖相迴路鎖入時間之量測 60
圖4.37　鎖定中心頻率2320MHz時鎖相迴路輸出訊號之相位雜訊 61
表4.1 壓控振盪器之規格表 …………………………………………………..43
表4.2 各差異積分調制器FPGA設計規格 44
表4.3　鎖入時間之量測 47
表4.4 相位頻率偵測器之模擬與量測規格比較表 52
表4.5 電荷幫浦之規格表 54
表4.6 多模除頻器之規格表 56
表4.7　壓控振盪器模擬與測量結果比較 58

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