本論文使用EDA工具輔助設計一應用於DVB-H系統之雙次轉頻架構射頻調諧器RFIC，同時利用TSMC 0.35um SiGe BiCMOS製程實現射頻調諧器RFIC之設計。為了熟悉EDA工具輔助RFIC設計與詳盡考量PCB效應之影響，本論文對於EDA工具之時域與頻域的分析方法做一深入探討，並且使用準靜態電磁軟體將PCB效應之等效電路萃取後再進行整合模擬。射頻調諧器之關鍵性元件，包含可變增益低雜訊放大器、升頻混波器、中頻放大器、降頻混波器等皆整合於單一晶片中，晶片操作於QPSK調制模式時擁有優越的靈敏度、寬廣的動態範圍與足夠的保護比例等表現，而且具有相當低之直流功率消耗，相當適合應用於行動數位電視廣播設備上。

This research aims to design a dual-conversion tuner RFIC for DVB-H applications with EDA tools. In order to have good understanding of the EDA tools used, both time-domain and frequency-domain simulation techniques are studied and discussed in this thesis. The designed tuner RFIC is implemented by a TSMC 0.35μm SiGe BiCMOS process. The parasitic effects from PCB interconnects are also considered in this work. We use 3-D quasi-static EM simulation tool to extract the parasitic elements for PCB interconnects, and co-simulate these parasitic elements with RFICs using circuit simulation tool. The implemented tuner RFIC integrates most key components into a single chip, including the variable-gain low noise amplifier, up-converting mixer, intermediate-frequency amplifier, and down-converting mixer. Under QPSK modulation test, the designed tuner RFIC shows a wide dynamic range with good protection ratio. In addition, it has a low power consumption and thus is suitable for use in portable digital TV equipments.

第一章 緒論
1.1 背景
1.2 手持式數位電視廣播系統
1.3 DVB-H系統射頻規格
1.4 章節介紹
第二章 射頻調諧器RFIC之架構研究與鏈路預算分析
2.1 射頻調諧器RFIC之系統架構
2.2 射頻調諧器RFIC之元件架構
2.3 DVB-H系統射頻調諧器鏈路預算分析
2.3.1 靈敏度分析
2.3.2 鄰近通道保護比例分析
第三章 DVB-H系統射頻調諧器RFIC設計
3.1 EDA工具分析方法探討
3.2 射頻元件設計
3.2.1 可變增益低雜訊放大器
3.2.2 升頻混波器
3.2.3 中頻放大器
3.2.4 降頻混波器
第四章 DVB-H系統射頻調諧器RFIC模擬與量測比較
4.1 射頻元件模擬與量測
4.1.1 可變增益低雜訊放大器
4.1.2 升頻混波器
4.1.3 中頻放大器
4.1.4 降頻混波器
4.2 DVB-H系統射頻調諧器RFIC之整合測試
4.2.1 連續訊號測試
4.2.2 動態範圍測試
4.2.3 鄰近通道保護比例測試
4.2.4 重疊通道保護比例測試
4.3 綜合討論
4.3.1 實驗結果討論
4.3.2 規格比較
第五章 結論
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