本論文共分三個部分。首先對相位雜訊於鎖相迴路的分析的與探討，由於OFDM系統升頻器需要良好相位雜訊的表現，所以本論文提出雙鎖相迴路之雜訊抑制架構，接著推導公式預測其電路特性。第二部分則是雙鎖相迴路之實驗與模擬，在實驗上藉著混成電路方式搭配相關的儀器與元件，可以量測到經雙鎖相迴路後之雜訊抑制效果，系統模擬上則利用ADS之元件行為模型。實驗與模擬結果相比較，在相位雜訊抑制的特性曲線變化上，兩者具有相當好的符合度。本論文最後利用台積電0.18μm CMOS製程設計一1.55-2.3 GHz可應用於DVB系統升-降電路架構之寬頻頻率合成器晶片，並針對此晶片性能作測試與討論，晶片功能符合設計目標。

This thesis is composed of three parts. In the first part, analysis and discussion of phase noise in phase-locked loop is made. Because OFDM upconverter requires high phase noise performance, we therefore study the mechanism of noise suppression in a proposed dual phase-locked loop, and then derive the formula to predict the circuit characteristics. In the second part, experiment and simulation of a dual phase-locked loop is performed for comparison. The experiment uses hybrid circuit combined with related equipment and components to measure the noise suppression characteristics in a dual phase-locked loop. The simulation relies on the component behavioral model in ADS. Comparison between simulation and measurement shows good agreement. In the third part, this thesis carries out a 1.55–2.3 GHz frequency synthesizer RFIC design for DVB up-down architecture using TSMC 0.18μm CMOS process. The test results validate the chip design.

第一章 序論 1
1.1 常見頻率合成器雜訊抑制機制 1
1.2 相位雜訊對OFDM系統的影響 3
1.3 章節規劃 5
第二章 雙鎖相迴路雜訊抑制分析 6
2.1 相位雜訊的定義 6
2.2 相位雜訊對OFDM系統的分析 9
2.3 整數式頻率合成器相位雜訊分析 10
2.4 雙鎖相迴路雜訊抑制機制分析 13
2.5 使用Matlab驗證數學理論模型 16
第三章 雙鎖相迴路之雜訊抑制實驗 22
3.1 相位偵測器 22
3.1.1 混波器 22
3.1.2 相位頻率偵測器 24
3.2 迴路濾波器設計 25
3.3 ADS模擬 28
3.3.1 頻率合成器模擬電路的建立 28
3.3.2 壓控振盪器之相位雜訊模型建立 29
3.3.3 ADS雜訊抑制模擬 30
3.4 實測討論 33
3.4.1. 振盪器的量測 33
3.4.2. 升頻鎖相迴路量測 34
3.4.3. 雙次轉頻升頻電路雜訊抑制量測 35
3.4.4. 架構優點比較 40
第四章 頻率合成器CMOS晶片設計 42
4.1 相位頻率偵測器 42
4.1.1 電路設計 42
4.1.2 模擬考量與結果 43
4.2 電荷幫浦 44
4.2.1 電路設計 44
4.2.2 模擬考量與結果 45
4.3 直接變數多模數除頻器 47
4.3.1 電路設計 47
4.3.2 模擬考量與結果 49
4.4 多頻帶雙點壓控振盪器 50
4.4.1 電路設計 50
4.4.2 模擬考量與結果 51
4.4.3 晶片電路規格與晶片佈局圖及照相圖 53
4.4.4 壓控振盪器和鎖相迴路的量測 54
4.4.5 鎖相迴路的量測 56
第五章 結論 60
參考文獻 61

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