本論文前半部份以CSR藍芽模組測試為主題，就發射端與接收端射頻規格進行測試。重點在藉由儀器之設定與操作，測試發射端之輸出功率、頻譜以及調制特性。接收端部份則著重在靈敏度與接收訊號強度指示之相關測試。論文後半部份為可以應用在藍芽系統之混合訊號積體電路設計，包括應用在鎖相迴路中之相位頻率偵測器、電流幫浦及除頻器等。另外設計可調截止頻率之轉導電容低通濾波器，主要應用在射頻與基頻介面電路上用來防止射頻端產生的贅餘訊號進入基頻端。

In the first part of this thesis, RF specifications of the CSR Bluetooth module were tested rigorously by means of proper equipment setup and manipulation. The tested parameters in the transmitter include output power, spectrum and modulation characteristics. The tested parameters in the receiver include sensitivity and received signal strength indicator. The second part of this thesis was mainly focused on some mixed-signal integrated-circuit designs that can be generally applied to the Bluetooth RF front-end. The design examples include the phase frequency detector, charge pump, and frequency divider in the applications of phase-locked loop. A transconductance-capacitor low-pass filter with tunable cut-off frequencies was also designed to suppress the spurious signals from RF front-end into baseband.

目錄 I
圖表目錄 II
第一章 緒論 1
第二章 藍芽射頻架構系統與射頻參數規格測試 3
2.1 藍芽傳收機射頻架構介紹 3
2.2 CSR藍芽系統射頻架構與其晶片規格介紹 6
2.3 CSR藍芽模組射頻規格測試 10
第三章 鎖相迴路與基頻低通濾波器之混合訊號積體電路設計 25
3.1 相位頻率偵測器 25
3.2 電流幫浦 ….33
3.3 雙模數除頻器 39
3.4 可調式基頻轉導電容低通濾波器 49
第四章結論 58
參考文獻 59

[1] B. Chatschik , “ An Overview of the Bluetooth Technology , “IEEE Comm-
unications Magazine, vol. 39, no. 12, pp. 86-94, Dec 2001.
[2] R. Shorey , ” The Bluetooth Technology : merits and limitations,” 2000
IEEE International Personal Wireless Communications Conference.
[3] A. A. Abidi, “Direct-conversion radio transceiver for digital
communications,” IEEE Journal of Solid-State Circuits, vol. 30,no. 12,pp.
1399-1410, Dec. 1995
[4] B. Razavi, RF Microelectronics, 1998.
[5] M.H. Perrott, T.L. Tewksbury III, C.G. Sodini, “A 27mW CMOS Fractional-N
synthesizer using digital compensation for 2.5-Mb/s GFSK Modulation,” IEEE
Journal of Solid-State Circuits, vol. 32, no.12, Dec1997.
[6] A.D. Riley, M.A. Copeland, “A Simplified Continuous phase modulator
technique,” IEEE Transactions on Circuits and Systems II : Analog and
Digital Signal Processing, vol. 41, no. 5, pp.321-328,May 1994
[7] W. Rhee, B.S. Song,A. Ali, “A 1.1-GHz CMOS Fractional-N Frequency
Synthesizer with a 3-b third-order Δ-Σ Modulator,” IEEE Journal of Solid-
State Circuits, pp.510-521, 1999
[8] A.D. Riley, M.A. Copeland, “Delta-Sigma Modulation in Fractional-N
Frequency Synthesis,” IEEE Journal Solid-State Circuits, pp.553-559, June
1991
[9] A. Mashhour, “On the Direct Conversion Receiver – A Tutorial,”IEEE
Microwave Journal, vol. 44, no. 6, pp.114-126, Jun 2001
[10] F. Bebahani, A.A. Abidi, “A 2.4GHz Low-IF Receiver for Wideband WLAN in
0.6μm CMOS Architecture and Front-End,” IEEE Journal Solid-State
Circuits, vol. 35, no. 12, pp.1908-1916, Dec 2000
[11] R.C. Chang, L.C. Kuo,”A differential type CMOS phase frequency
detector,” Proceedings of the Second IEEE Asia Pacific Conference, pp.61-
64
[12] H.O. Johansson, “A Simple precharge CMOS phase frequency detector,” IEEE
Journal of Solid-State Circuits, vol. 33, no. 2, Feb. 1998
[13] E.J. Hernandez, A.D. Sanchez, “Positive Feed-back CMOS charge-pump
circuits for PLL Applications,” Proceedings of the 44th IEEE 2001 Midwest
Symposium, vol. 2 , pp.836-839, 2001
[14] N. Adachi, A. Inoue, K. Yamashita, “PLL frequency synthesizer for TDMA
systems,” 1995 Fourth IEEE International Conference Universal Personal
Communications, pp.316-320, 1995
[15] J. Craninckx, M.S. Steyaert, “A 1.75-GHz/3-V dual-modulus divide –by-
128/129 prescaler in 0.7μm CMOS,” IEEE Journal of Solid-State Circuits,
vol. 31, no. 7,July 1997
[16] C.Y. Yang, G.K. Dehng, J.M. Hsu, S.I. Liu, “ New dynamic flip-flops for
high-speed dual-modulus prescaler,” IEEE Journal of Solid-State Circuits,
vol. 33 , no. 10, Oct 1998
[17] A.C. Carusone, D.A. Johns, “A 5th order Gm-C filter in 0.25μm CMOS with
digitally programmable poles and zeros,” 2002 IEEE International Circuits
and Systems Symposium , vol. 4, pp.635-638, 2002
[18] J. Lee, K. Hayatleh, F.J. Lidgey, J. Drew, “Tuneable linear transconduct
tance cell for Gm-C filter applications,” 2002 IEEE International
Circuits and Systems Symposium
[19] Naess, Y. Berg, “Tunable ultralow voltage transconductance amplifier and
Gm-C filter,” The 2000 IEEE Circuits and Systems International Symposium,
vol. 2, pp.709-712, 2000
[20] Y. Changsik, S.W. Lee, W. Kim, “ A 1.5-V, 4-MHz CMOS continuous time
filter with a single-integrator based tuning,” IEEE Journal of Solid-
State Circuits, vol. 33, no. 1, Jan 1998
[21] C.C. Huang, K.A.I. Halonen, M. Ismail, V. Porra, A. Hyogo, “A low
voltage, low-power CMOS fifth-order elliptic GM-C filter for baseband
mobile, wireless communication,” IEEE Transactions on Circuits and
Systems for Video Technology, vol. 7, no. 4, Aug 1997