本論文主要實踐一兼具高效率與高線性度之射頻發射機。以座標旋轉數位演算法在FPGA上實現一極座標轉換單元，取代傳統波包消除重建架構中的波包偵測器與限制器，不僅具有更精確的調制品質並且適合於單晶片系統。波包路徑以一階差異積分調制配合高效率切換式直流轉換器可高效率地放大波包訊號，配合E類功率放大器之輸出電壓與供應電壓間具有良好的線性關係，使極座標調制發射機可同時兼具高效率與高線性度。此外，提出一雙端時變調制發射機架構，在E類功率放大器射頻輸入端施予IQ調制而在供應電壓端施予波包調制，配合動態輸入功率控制操作，可使發射機之轉換效率或線性度都幾乎能與輸出功率無關。以實際傳送1.2288 Msps QPSK之CDMA2000 1x訊號為例，發射機在輸出功率為10~22 dBm之範圍內，汲極效率約為48 %，ACPR約為47 dB，EVM約為6 %。

Abstract：

This thesis mainly implemented an RF transmitter with high efficiency and high linearity. A Cartesian to Polar transformation was implemented by CORDIC algorithm using FPGA. By replacing the envelope detector and limiter in traditional envelope elimination and restoration transmitter, this technique not only achieves more accurate modulation quality, but also becomes more suitable for single chip system. Applying the first order delta-sigma modulation and highly efficient switching-mode DC converter, the envelope signal was amplified highly efficiently. Due to the class-E power amplifier having good linear relation between output voltage and supply voltage, the polar modulation transmitter can achieve high efficiency and high linearity simultaneously. Furthermore, this thesis purposed a new transmitter with two-terminal time-varying modulation. The IQ modulated signal was fed to the input terminal of class-E amplifier, while the envelope signal was used to amplitude modulate the voltage supply terminal. With dynamic input power control, the conversion efficiency and linearity are independent of output power in the purposed architecture. From the experimental results, while transmitting a QPSK-modulated CDMA2000 1x signal with 1.2288 Msps data rate, the transmitter achieve 48 % in drain efficiency, 47 dB in ACPR, and 6 % in EVM at the output power ranging from 10 to 22 dBm.

第一章 緒論
1.1 背景簡介
1.2 章節規劃
第二章 基頻數位電路設計
2.1 基頻數位電路架構
2.2 採用CORDIC演算法之波包與相位分離單元
2.2.1 CORDIC演算法原理
2.2.2 CORDIC演算法模擬
2.3 CDMA2000 1x 數位濾波器
2.4 半頻帶濾波器
2.5 線性內插器
2.6 微分器
2.7 一階差異積分調制器
2.8 基頻數位電路之系統模擬
2.9 數位類比轉換器模組
2.10 實驗結果
第三章 波包路徑之切換式直流轉換器晶片設計
3.1 互補切換式直流轉換器之架構
3.2 設計方法與模擬結果
3.2.1 設計流程
3.2.2 切換式直流轉換器模擬
3.3 切換式直流轉換器晶片量測
第四章 1.95 GHz之E類功率放大器設計
4.1 E類功率放大器之架構
4.2 E類功率放大器積體電路設計與量測
4.2.1 設計流程
4.2.2 模擬與量測結果
4.3 應用於極座標與雙端時變調制架構之線性度與效率量測
第五章 高效率線性發射機之實驗結果
5.1 極座標調制架構之發射機量測
5.1.1 理想波包訊號下之極座標調制發射機量測
5.1.2 實際波包訊號下之極座標調制發射機量測
5.2 雙端時變調制架構之發射機量測
5.2.1 理想波包訊號下之雙端時變調制發射機量測
5.2.2 實際波包訊號下之雙端時變調制發射機量測
5.3 動態輸入功率控制之極座標調制發射機量測

第六章 結論
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