本論文前半段推導了差異積分調制器量化雜訊模型，並轉換為相位雜訊以估計差異積分調制器對於分數式頻率合成器雜訊之影響。在差異積分調制器架構方面，則分別對於多級雜訊整形與單迴路二種架構做深入的探討，並比較二種差異積分調制器架構置入於分數式頻率合成器中的優缺點，以作為設計時之參考。論文後半段則實現了一個採用單迴路差異積分調制器之分數式頻率合成器，利用設計Verilog HDL程式碼並下載至FPGA以實現一個具有16 bits訊號解析度之單迴路差異積分調制器，與頻率合成器模組結合後，完成一個頻率範圍為2400~2500 MHz之分數式頻率合成器，具有183 Hz之頻率解析度。在相位雜訊表現上，在頻率位移10 kHz處，相位雜訊小於 -54 dBc/Hz，相較於相同階數之多級雜訊整型架構，雜訊可改善10至12dB。除此之外，頻率跳躍48 MHz之相位鎖入時間小於29 us。

This thesis establishes a quantization noise model of a delta-sigma modulator (DSM), which is utilized to estimate the phase noise performance of a fractional-N frequency synthesizer. In delta-sigma modulator structures, we choose multi-stage noise shaping (MASH) and single-loop structure for investigating the advantages and disadvantages.
We have implemented a 3rd order single-loop and a 3rd order MASH DSM by using Verilog codes and a Xilinx field-programmable gate-array (FPGA). With a reference frequency of 12MHz, the fractional-N frequency synthesizer has an output frequency band of 2400~2500MHz, and a frequency resolution of 183 Hz. The measured phase noise is lower than -54 dBc/Hz at 10 kHz offset frequency. The PLL settling time is less than 29us with a 48 MHz frequency hopping.

第一章 緒論
1.1 簡介
1.2 章節規劃
第二章 鎖相迴路頻率合成器
2.1 整數式頻率合成器
2.2 整數式頻率合成器之雜訊分析
2.3 分數式頻率合成器
2.4 運用差異積分調制器之分數式頻率合成器
第三章 差異積分調制器
3.1 差異積分調制原理
3.2 一階差異積分調制器
3.3 高階差異積分調制器
3.4 差異積分調制器對相位雜訊的影響
3.5 多級雜訊整形架構
3.6 單迴路架構
第四章 採用單迴路差異積分調制器之分數式頻率合成器製作與量測
4.1 單迴路差異積分調制器之模擬與設計
4.1.1 雜訊傳輸函數之設計
4.1.2 量化器之設計
4.2 單迴路差異積分調制器之實作與驗證
4.2.1 Verilog HDL程式碼設計
4.2.2 數位電路實現與量測
4.3 分數式頻率合成器製作
4.3.1 迴路濾波器
4.3.2 鎖相迴路設計
4.4 單迴路差異積分調制器結合分數式頻率合成器測試
第五章 結論
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