雙邊沿觸發正反器(DETFF) 提供了一種降低時脈頻率，並保持相同數據吞吐量，用以降低功耗的解決方案。另外，網路和無線通信的發展使得可靠度比以往任何時候都更加重要，因此本論文提出一種低功耗的移位暫存器與寬頻帶隨機亂數產生器之設計，以提供資安所需之金鑰。
本論文第二章中，我們提出一DETFF 的8 位元低功耗移位暫存器的設計，主要貢獻是利用了兩個並行數據路徑，這些路徑在沒有反相輸入正反器的情況下，以單一反相時脈進行工作。本章之移位暫存器設計是以TSMC 90-nm CMOS 製程實現。佈局後模擬結果顯示，本章提出的移位暫存器可在100 MHz 時脈下，至少降低了17.2 % 的功耗，且晶片測量結果則證明本章之暫存器遠優於所有其他先前文獻。
本論文第三章提出了一種寬頻帶亞穩態隨機亂數產生器，其為類比與數位隨機亂數產生器所設計的混合電路。類比亂數種子產生器與瞬態效應環形振盪器(TERO) 相結合，以保持信息的高度隨機性。為了保持更高的可靠度，兩種模組連接到一個多工器，在輸出端獲得高亂度的數據。此隨機亂數產生器以TSMC 40-nm CMOS 製程實現，佈局後模擬顯示帶寬為50 MHz。

Double-edge triggered flip-flops (DETFF) project a solution to power reduction by lowering the clock frequency and maintaining the same data throughput. The development of network and wireless communications has made the security more important than ever. So, this thesis presents a low power consuming shift register and wide bandwidth random number generator design. In Chapter 2, an 8-bit low power shift register by using a newly designed DETFF is illustrated. The significant contribution of this work takes advantage of two parallel data paths that work in inverse periods of the single clock without an inverted input trigger. A common 90-nm CMOS process is utilized to design the proposed shift register configuration. The post-layout simulation results show that the proposed shift register decreases the power consumption by at least 17.2 % at 100 MHz clock rate. The on chip silicon measurement results show that not only the proposed design is proved fully functional at 200 MHz, the figure of merit is also far better than all other prior works.
A wide bandwidth metastable random number generator has been proposed in Chapter 3. This design is a mixture of analog and digital RNGs. An analog seed generator combined with a transient effect ring oscillator (TERO) to maintain high randomness of the information. To maintain more security, these two modules are connected to a multiplexer to get highly encrypted data at the output end. A typical TSMC 40-nm process has been implemented to realize this design. Post-layout simulations show that the bandwidth is 50 MHz.

論文審定書. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Thesis Validation Letter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
論文摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
1 Introduction and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Low power shift register . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Random number generator . . . . . . . . . . . . . . . . . . . . . 3
1.1.3 Goals of This Thesis . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 Low Power DETFF . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.2 Random Number Generator . . . . . . . . . . . . . . . . . . . . 6
1.3 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 A Low-Power 8-Bit Shift Register Using Double Edge Trigger Flip-flop . . . . 11
2.1 Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Circuit Analysis of Low Power DETFF . . . . . . . . . . . . . . . . . . 11
2.2.1 Power Analysis of DETFF . . . . . . . . . . . . . . . . . . . . . 13
2.2.2 Transistor Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 Architecture of 8-bit Shift Register Using DETFF . . . . . . . . . . . . . 17
2.4 Circuit Simulations and Performance Prediction . . . . . . . . . . . . . . 17
2.4.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Chip Implementation and Measurement . . . . . . . . . . . . . . . . . . 21
2.5.1 Measurement Environment . . . . . . . . . . . . . . . . . . . . . 21
2.5.2 Measurement of 8-bit shift register . . . . . . . . . . . . . . . . . 22
2.5.3 Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5.4 Jitter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.6 Measurement Comparison . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.6.1 Circuit specification and comparison . . . . . . . . . . . . . . . . 27
2.6.2 Comparison with Prior Works . . . . . . . . . . . . . . . . . . . 30
2.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3 High Bandwidth Metastable Random Number Generator . . . . . . . . . . . . 34

3.1 Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2 System Architecture of the proposed Random Number Generator (RNG) . 34
3.2.1 Transient Effect Ring Oscillator (TERO) . . . . . . . . . . . . . 35
3.3 Chip Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4 Simulations and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4.1 Monobit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.4.2 Long Run test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.5 Comparison with prior works . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5.1 Circuit specification and comparison . . . . . . . . . . . . . . . . 41
3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.1 Conclusion and Achievements . . . . . . . . . . . . . . . . . . . . . . . 44
4.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2.1 Low Power DETFF . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2.2 RNG with Analog Seed Generator . . . . . . . . . . . . . . . . . 46
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

[1] A. Baskoro, O. Setyawati, P. Siwindarto, and C.-C. Wang, “Low-power high-speed
8-bit shift register using double-edge triggered flip-flops,” in Proc. 8th International
Workshop on Computer Science and Engineering (WCSE), pp. 151–153, June 2018.
[2] C.-C. Wang and S.-W. Lu, “100 MHz random number generator design using interleaved
metastable NAND/NOR latches*,” in Proc. IEEE Asia Pacific Conference
on Circuits and Systems (APCCAS), pp. 98–101, May 2020.
[3] C.-C. Yu and C.-C. Tsai, “Dual edge-triggered D-type flip-flop with low power consumption,”
International Journal of Computer Science and Information Technology
(IJCSIT), vol. 10, no. 5, pp. 01–12, Nov. 2018.
[4] S. K. Tawfeeq, “A random number generator based on single-photon avalanche photodiode
dark counts,” Journal of Lightwave Technology, vol. 27, no. 24, pp. 5665–
5667, Dec. 2009.
[5] K. Siddhant, G. Singh, and V. Sulochana, “A low power 32-bit CMOS ROM using a
novel ATD circuit,” International Journal of Electrical and Computer Engineering
(IJECE), vol. 3, no. 4, pp. 509–515, Aug. 2013.
[6] R. Sharma and B. Singh, “Design and analysis of linear feedback shift register
(LFSR) using gate diffusion input (GDI) technique,” in Proc. 5th International Conference
on Wireless Networks and Embedded Systems (WECON), pp. 1–5, Oct. 2016.
[7] C.-C. Wang, G.-N. Sung, M.-K. Chang, and Y.-Y. Shen, “Energy-efficient double-edge
triggered flip-flop design,” in Proc. IEEE Asia Pacific Conference on Circuits
and Systems (APCCAS), pp. 1791–1794, Dec. 2006.
49
[8] R. Hossain, L. Wronski, and A. Albicki, “Low power design using double edge triggered
flip-flops,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 2, no. 2, pp. 261–265, June 1994.
[9] T. Amaki, M. Hashimoto, and T. Onoye, “A process and temperature tolerant
oscillator-based true random number generator with dynamic 0/1 bias correction,”
in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 133–136, Nov.
2013.
[10] A. J. Menezes, S. A. Vanstone, and P. C. V. Oorschot, Handbook of Applied Cryptography.
USA: CRC Press, Inc., 1st ed., 1996.
[11] T. Johnson and I. Kourtev, “A single latch, high speed double-edge triggered flipflop
(DETFF),” in Proc. 8th IEEE International Conference on Electronics, Circuits
and Systems (ICECS), vol. 1, pp. 189–192, Sep. 2001.
[12] C.-C. Wang, C.-J. Huang, and K.-C. Tsai, “A 1.0-GHz 0.6-μm 8-bit carry lookahead
adder using PLA-styled all-N-transistor logic,” IEEE Transactions on Circuits and
Systems II: Analog and Digital Signal Processing, vol. 47, no. 2, pp. 133–135, Feb.
2000.
[13] A. Tyagi, N. Pandey, and K. Gupta, “PFSCL based linear feedback shift register,”
in Proc. International Conference on Computational Techniques in Information and
Communication Technologies (ICCTICT), pp. 580–585, Mar. 2016.
[14] Y.-Y. Sung and R. Chang, “A novel CMOS double-edge triggered flip-flop for lowpower
applications,” in Proc. IEEE International Symposium on Circuits and Systems
(ISCAS), vol. 2, pp. 665–668, May 2004.
50
[15] Y. Praveen Kumar, B. Kariyappa, and M. Kurian, “Implementation of power efficient
8-bit reversible linear feedback shift register for BIST,” in Proc. International
Conference on Inventive Systems and Control (ICISC), pp. 1–5, Jan. 2017.
[16] A. Bagalkoti, S. B. Shirol, S. Ramakrishna, P. Kumar, and B. S. Rajashekar, “Design
and implementation of 8-bit LFSR, bit-swapping LFSR and weighted random test
pattern generator: a performance improvement,” in Proc. International Conference
on Intelligent Sustainable Systems (ICISS), pp. 82–86, Feb. 2019.
[17] T.-S. Li, L.-J. Wu, X.-M. Zhang, X.-J. Wu, J. Zhou, and X.-L. Wang, “A novel
transition effect ring oscillator based true random number generator for a security
SoC,” in Proc. International Conference on Electron Devices and Solid-State Circuits
(EDSSC), pp. 1–2, Oct. 2017.
[18] C.-C. Wang, J.-M. Huang, H.-C. Cheng, and R. Hu, “Switched-current 3-bit CMOS
4.0-MHz wideband random signal generator,” IEEE Journal of Solid-State Circuits,
vol. 40, no. 6, pp. 1360–1365, June 2005.
[19] Y. Yang, G. Bai, and H. Chen, “A 200 Mbps random number generator with jitteramplified
oscillator,” in Proc. Fifth International Conference on Computing, Communications
and Networking Technologies (ICCCNT), pp. 1–5, July 2014.
[20] M. Siswanto and B. Rudiyanto, “Designing of quantum random number generator
(QRNG) for security application,” in Proc. 3rd International Conference on Science
in Information Technology (ICSITech), pp. 273–277, Oct. 2017.
[21] P. Zode, P. Zode, and R. Deshmukh, “FPGA based novel true random number generator
using LFSR with dynamic seed,” in Proc. IEEE 16th India Council International
Conference (INDICON), pp. 1–3, Dec. 2019.
51
[22] C.-Y. Huang, W. C. Shen, Y.-H. Tseng, Y.-C. King, and C.-J. Lin, “A contactresistive
random-access-memory-based true random number generator,” IEEE Electron
Device Letters, vol. 33, no. 8, pp. 1108–1110, June 2012.
[23] C. Petrie and J. Connelly, “A noise-based IC random number generator for applications
in cryptography,” IEEE Transactions on Circuits and Systems I: Fundamental
Theory and Applications, vol. 47, no. 5, pp. 615–621, Dec. 2000.
[24] G. Liu, L. He, X. Xue, and Q. Shi, “A new current switch driver with improved
dynamic performance used for 500 MS/s, 12-bit Nyquist current-steering DAC,” in
Proc. 9th IEEE International Conference on ASIC, pp. 496–499, Oct. 2011.
[25] C.-H. Chu, A Broken Line Detection and Aging Protection Circuit for Multi-cell Li-ion
Battery Pack and Low Power 8-bit Shift Register Using Double-Edge triggered
Flip-Flop. M. S. Thesis, NSYSU, July 2020.
[26] TechTarget, What is Jitter? & What causes Jitter? [Online]. Available: https://
searchunifiedcommunications.techtarget.com/definition/jitter.
[27] B. Acar and S. Ergun, “A reconfigurable random number generator based on the
transient effects of ring oscillators,” IEEE Transactions on Circuits and Systems II:
Express Briefs, vol. 67, no. 9, pp. 1609–1613, July 2020.
[28] U. K. N. Ekkurthi, V. Dasari, J. Akiri, and C.-C. Wang, “A 100 MHz 9.14-mW 8-
bit shift register using double-edge triggered flip-flop,” in Proc. IEEE International
Symposium on Circuits and Systems (ISCAS), pp. 1–4, May 2021.