這一篇論文主要探討兩種型態的射頻金屬氧化型低雜訊放大器：分別為 (1)低功率金屬氧化型低雜訊放大器及 (2)影像抑制金屬氧化型低雜訊放大器。
此篇文章將深入的探討影像抑制金屬氧化型低雜訊放大器的增益、雜訊指數和穩定度。經由此研究, 我們可以用簡單但深含物理的觀念描述具影像抑制金屬氧化型低雜訊放大器的基本特性。
接著，我們也提出一種低電流的源極退化串極串基型金屬氧化型低雜訊放大器，藉由使用N通道金屬氧化型電晶體形式之源極退化反向器，來改善低雜訊放大器的增益、雜訊指數。此低雜訊放大器擁有最佳低雜訊放大器之結構。從設計的觀點來看，此放大器可輕易的最佳化，得設計變的簡單且容易。
此外，藉由改進提出之低電流的源極退化串極串基型金屬氧化型低雜訊放大器，不需要額外加入影像抑制之濾波器，此放大器自然擁有影像抑制之功能，相較於傳統的架構，此架構有低功率、低雜訊和高影像抑制之特性，適用於低功率射頻接收機。
最後，除了電晶體工作於中反轉層之雜訊評估外，我們使用台積電射頻金屬氧化型元件模型模擬此兩種放大器。低電流雜訊放大器擁有0.7 dB之雜訊指數，16 dB之增益和IIP3為 -16 dBm之特性。影像抑制電流雜訊放大器擁有0.7 dB之雜訊指數，16 dB之增益和IIP3為 -15 dBm之特性，在影像頻率為1.6 GHz上，有20 dB之影像抑制之能力。此兩種放大器皆操作在2.5 V之電源，同時各別消耗6 mA之電流。

This thesis deals with two kinds of RF CMOS low noise amplifiers (LNA). The low power LNA and the image-reject LNA.
The impact of gain, noise figure, and stability on RF CMOS image-reject LNA has been studied. Through this study, the fundamental properties of image-reject LNA can be understood by a simple but physical concept.
A current-reuse RF CMOS source-degenerated cascode LNA is also presented, which adopts a combination of source-degenerated NMOS inverter and Cascode topology to improve gain and noise figure, the existent and well-studied technique from the design standpoint, makes optimization of the stage easy.
A modification of the proposed architecture is also presented, which adopts internal filters to achieve the image rejection without additional image-reject filters that degrade both noise figure and power consumption. It will be a good candidate for low power implementation of CMOS RF-IC.
Both circuits’ parameters except noise figures are simulated using TSMC 0.25 um RF CMOS component models. The noise models considered here include induced gate noise, thermal noise and shot noise [5]. The current-reuse source-degenerated NMOS inverter LNA noise figure is 0.7 dB, forward gain is 16 dB, and IIP3 is -15 dBm. The low power image-reject LNA noise figure is 0.7 dB, forward gain is 16 dB, IIP3 is -16 dBm, and image rejection is 20 dB at 1.6 GHz. Both LNAs operate at 2.4 GHz and consume about 6 mA under a 2.5 V voltage supply.

Chapter 1 Introduction 1

1.1 Architectures of Inductively Degenerated CMOS LNA 3
1.2 Optimization Techniques for Source-Degenerated cascode CMOS LNA 4
1.3 The Problem of Image 5

Chapter 2 Image-Reject LNA 8

2.1 Input Matching 8
2.2 Input Matching (with Cgd included) 12
2.3 Gain 14
2.4 Gain (with Cgd included) 17
2.5 Image Rejection and Stability 18
2.6 Noise Figure 19
2.7 The Impact of Gate Noise for LNA 22
2.8 Noise Figure versus Gate Width 23
2.9 Noise Figure versus Quality Factor of the Notch filter 24

Chapter 3 Current Reuse Techniques For RF CMOS Cascode LNAs 25

3.1 Introduction 25
3.2 Current Reuse Techniques for RF CMOS LNAs 26
3.3 Proposed Current Reuse technique by Using NMOS Inverter 27
3.4 Image-Reject Techniques for CMOS LNAs 31
3.5 Image-Reject Technique by Modifying the proposed Current-Reuse LNA 33
3.6. Simulation results 35

Chapter 4 Conclusion 39

Appendix A Some Useful Simulated programs (Frequency response)
Appendix B A linear System with a Random Input Signal
Reference

1. H. Samavati, H. R. Rategh, T. H. Lee, "A 5-GHz CMOS wireless LAN receiver front end", IEEE J. Solid-State Circuits, vol.35, pp.765 -772, May 2000.
2. D. K. Shaeffer, T. H. Lee, "A 1.5-V 1.5-GHz CMOS low noise amplifier ", IEEE J. Solid-State Circuits, vol.32, pp.745 -759, Mar. 1997.
3. Jung-Suk Goo ,”A noise optimization technique for integrated low-noise amplifiers”, IEEE J. Solid-State Circuits, vol.37, pp.994-1002, Aug. 2002.
4. A. N. Karanicolas, "A 2.7-V 900-MHz CMOS LNA and mixer", IEEE J. Solid-State Circuits, vol.31, Dec. 1996.
5. Gatta, F.”A 2-dB noise figure 900-MHz differential CMOS LNA”,IEEE J. Solid-State Circuits,Vol.36 Issue: 10 , Oct 2001
6. Fouad, H.Sharaf, K.;El-Diwany,E.El-Hennawy, "An RF CMOS cascode LNA with current reuse and inductive source degeneration".;Circuits and Systems, 2001 MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on ,Volume: 2 , 2001 Page(s): 824 -828 vol.2
7. "TQ9203—Low current RFIC downconverter", TriQuint Semiconductor, Inc, 1995.
8. Cha, Lee, "A 5.2-GHz LNA in 0.35-$mu$m CMOS utilizing inter-stage series resonance and optimizing the substrate resistance", Proc. Eur. Solid State Circuits Conf., pp.339-342, Sept. 2002.
9. J. Macedo, M. Copeland, "A 1.9-GHz silicon receiver with monolithic image filtering",IEEE J. Solid-State Circuits, vol.33, pp.378-386, Mar. 1998.
10. Foley, B.; Murphy, P.;Murphy, A. "A monolithic SiGe 5 GHz low noise amplifier and tuneable image-reject filter for wireless LAN applications";High Frequency Postgraduate Student Colloquium, 2000 ,Page(s): 26-31
11. Moneim Youssef, A.A.; Sharaf, K.; "Vlsi design of CMOS mage-reject LNA for 950-MHz wireless receivers "; Circuits and Systems for Communications, 2002. Proceedings. ICCSC '02. 1st IEEE International Conference on , 2002 Page(s): 330 -333
12. Jung-Suk Goo ,”A noise optimization technique for integrated low-noise amplifiers”, IEEE J. Solid-State Circuits, vol.37, pp.994-1002, Aug. 2002.
13. Hossein Hashemi,”Concurrent Multiband Low Noise Amplifiers-Theory,Design,and Applications”IEEE Transaction On Microwave Theory .Vol,50.No1.January 2002.
14. Abou-Allam, E.; Nisbet, J.J.; Maliepaard, M.C, “Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology”, IEEE J. Solid-State Circuits, vol.36, pp.345 -359, Oct. 2001.
15. Enz, Chen, "MOS transistor modeling for RF IC design", IEEE J. Solid-State Circuits, vol.35, pp.186-201, Feb. 2000 .
16. Enz, C.; "An MOS transistor model for RF IC design valid in all regions of operation"IEEE Transaction On Microwave Theory .Vol,50.No1.January 2002.