本論文主要分為三部份，第一部分主要是探討現今應用於DVB-H系統調諧器的射頻架構與所採用的半導體製程技術，並選擇適當的射頻架構與製程進行RFIC設計。第二部份則利用TSMC 0.18μm RF CMOS製程，實際設計該系統調諧器之RFIC，並詳細說明各級電路的設計與實測結果。第三部份則是針對所設計之RFIC進行整合測試，測試項目包含連續訊號測試以及DVB-H標準訊號測試。本RFIC在8MHz通道頻寬之2K模式以及QPSK數位調制且編碼率為7/8條件下，進行DVB-H標準調制訊號測試。測試結果RFIC具有-87dBm的靈敏度，鄰近通道保護比例符合規範要求。晶片功率消耗為70.2mW且面積為1.96 mm2。

This thesis is composed of three parts. The first part surveys the literature on RF architecture and semiconductor process technology in the DVB-H tuner applications. The RFIC design considerations are also discussed. In the second part, the DVB-H tuner RFIC design using TSMC 0.18μm RF CMOS technology is presented. Discussions between simulated and measured results of each circuit stage are also included. In the third part, the RFIC testing results for CW and DVB-H input signals are demonstrated. For a QPSK signal with 8MHz bandwidth and 7/8 code rate, the sensitivity of the RFIC can reach -87dBm. The adjacent channel protection ratio can meet the specification. The chip power consumption is 70.2mW, and the chip size is 1.96 mm2.

第一章 緒論 1
1.1 半導體製程技術的發展背景 1
1.2 手持式數位電視廣播系統 3
1.3 研究動機 4
1.4 章節介紹 5
第二章 射頻調諧器RFIC之架構分析與製程選擇 6
2.1 射頻調諧器射頻架構 6
2.1.1 雙次轉頻式架構 6
2.1.2 直接轉頻式架構 7
2.1.3 雙次轉頻第二零中頻架構 8
2.2 射頻調諧器關鍵元件電路架構 9
2.2.1 低雜訊可變增益放大器 9
2.2.2 升頻混波器 12
2.2.3 正交解調器 13
2.3 DVB-H系統的射頻調諧器RFIC架構與製程選擇 15
第三章 DVB-H系統射頻調諧器RFIC之設計 17
3.1 低雜訊可變增益放大器 18
3.2 升頻混波器 24
3.3 正交解調器 30
第四章 DVB-H系統射頻調諧器RFIC之整合測試 41
4.1 射頻調諧器RFIC鏈路預算分析 41
4.1.1 靈敏度預估 42
4.1.2 鄰近通道保護比例預估 43
4.2 射頻調諧器RFIC之整合測試 44
4.2.1 連續訊號測試 44
4.2.2 標準調制訊號之動態範圍測試 46
4.2.3 鄰近通道保護比例測試 62
4.2.4 重疊通道保護比例測試 70
4.3 綜合討論 72
4.3.1 實驗結果討論 72
4.3.2 規格比較 73
第五章 結論 76
參考文獻 77
附錄一 DVB-H標準調制訊號準確度測試 i

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