在採用差異積分調制器之分數式頻率合成器中，為了提高鎖入速度，則必須增加迴路頻寬，但增加迴路頻寬會引入更多量化雜訊，造成相位雜訊表現變差，因此鎖入時間與相位雜訊表現為取捨的關係。為了研究改善方法，本論文研究量化雜訊抵銷技術，企圖使迴路頻寬增加並且能同時維持好的相位雜訊的表現。研究過程中利用安捷倫公司所研發的模擬軟體ADS來輔助預測量化雜訊抵銷技術對頻率合成器之相位雜訊改善效果。實作部分，本論文實際完成2.6GHz分數式頻率合成器hybrid模組，在使用不同階數之MASH差異積分調制器，並且改變鎖相迴路頻寬條件下量測量化雜訊抵銷技術對相位雜訊之改善效果。論文中也利用台積電0.18μm CMOS製程設計一鎖相迴路晶片，並針對此晶片性能作測試與檢討。

For the fractional-N frequency synthesizers using delta-sigma modulation (DSM) techniques, higher PLL bandwidth is highly desirable in order to achieve faster settling time. As the PLL bandwidth is increased, more quantization noises pass through the PLL so that the output phase noise performance is degraded. There is a tradeoff between phase-noise performance and PLL bandwidth. To improve the problem, the thesis studies the quantization noise cancellation technique. With this technique, the PLL bandwidth can be increased without the cost of degrading phase-noise performance. With the help of Agilent EEsof’s ADS, the phase-noise performance of the studied fractional-N frequency synthesizers can be predicted. For demonstration, this research implements a 2.6 GHz fractional-N frequency synthesizer hybrid module, and compares the measured phase noises with and without the technique under considering various combinations of MASH DSM orders and PLL bandwidth. Another demonstration of this thesis is to design a PLL IC using TSMC 0.18 μm CMOS process, and make a discussion on the testing performance of the PLL IC.

第一章 序論...................................................................................................1
1.1 簡介............................................................................................................. 1
1.2 章節規劃..................................................................................................... 4
第二章 分數式頻率合成器架構與量化雜訊抵銷技術..................................5
2.1 分數式頻率合成器的架構與操作原理....................................................... 5
2.2 採用差異積分調制之分數式頻率合成器................................................... 7
2.2.1 多級雜訊整形架構.......................................................................... 8
2.2.2 單迴路架構................................................................................... 10
2.2.3 非線性效應分析............................................................................ 13
2.3 量化雜訊抵銷技術之理論分析與模擬..................................................... 15
2.3.1 量化雜訊抵銷技術理論分析......................................................... 15
2.3.2 量化雜訊抵銷技術理論模擬......................................................... 18
2.4 運用量化雜訊抵銷技術之分數式頻率合成器軟體輔助模擬.................. 19
2.4.1 系統模擬環境................................................................................ 20
2.4.2 頻率合成器模擬電路之建立......................................................... 21
2.4.3 壓控振盪器行為模型之建立......................................................... 22
2.4.4 差異積分調制器與量化誤差抵銷模擬電路之建立...................... 22
2.4.5 量化雜訊抵銷技術對於相位雜訊之改善..................................... 23
第三章 2.6GHz 鎖相迴路CMOS 電路設計...............................................26
3.1 多模數除頻器........................................................................................... 26
3.1.1 多模數除頻器設計........................................................................ 26
3.1.2 模擬考量與結果............................................................................ 30
3.2 相位頻率偵測器....................................................................................... 32
3.2.1 相位頻率偵測器設計.................................................................... 32
3.2.2 模擬考量與結果............................................................................ 33
3.3 電荷幫浦................................................................................................... 35
3.3.1 電荷幫浦設計................................................................................ 35
3.3.2 模擬考量與結果............................................................................ 36
3.4 壓控振盪器............................................................................................... 38
3.4.1 壓控振盪器設計............................................................................ 38
3.4.2 模擬考量與結果............................................................................ 39
第四章 量化雜訊抵銷技術之實作驗證與鎖相迴路電路晶片之測試........42
4.1 分數式頻率合成器模組之實作................................................................ 42
4.1.1 PE3335 IC 功能簡介..................................................................... 43
4.1.2 被動迴路濾波器之實作................................................................ 44
4.1.3 雙點壓控振盪器之實作................................................................ 45
4.1.4 電壓電流轉換器之實作................................................................ 47
4.1.5 差異積分調制器之實作................................................................ 50
4.2 運用量化雜訊抵銷技術之分數式頻率合成器模組量測.......................... 51
4.3 CMOS 鎖相迴路晶片之量測................................................................... 56
4.3.1 相位頻率偵測器之量測................................................................ 57
4.3.2 電荷幫浦之量測............................................................................ 59
4.3.3 多模數除頻器之量測.................................................................... 62
4.3.4 雙點壓控振盪器之量測................................................................ 63
第五章 結論.................................................................................................65
參考文獻.......................................................................................................66

[1]H. Huh,et.al., “A CMOS dual-band fractional-N synthesizer with reference doubler and compensated charge pump,” in IEEE Int. Solid-State Circuits Conference, pp.100-101, Feb. 2004.
[2]T. A. D. Riley, N. M. Filiol, D. Qinghong, and J. Kostamovaara, “Techniques for in-band phase noise reduction in Delta-Sigma synthesizers,” IEEE Tran. Circuits and Systems II: Analog and Digital Signal Processing, pp. 794-803, Nov. 2003.
[3]R. Dehghani, “A 2.5 GHz CMOS fully-integrated Delta-Sigma controlled fractional-N frequency synthesizer,” in Proc. IEEE Int. Conf. VLSI Design, 2004, pp. 163-167.
[4]B. De Muer and M. S. J. Steyaert, “A CMOS monolithic Delta-Sigma controlled fractional-N frequency synthesizer for DCS-1800,” IEEE J. Solid-State Circuits , pp. 835-844, July 2002.
[5]何文豪，採用單迴路差異積分調制器之分數式頻率合成器，國立中山大學電機工程研究所碩士論文，2005。
[6]C. J. Li, T. S. Horng, C. H.Hung, and K. C. Peng, “Incorporating the single-loop delta-sigma modulator in a fractional-N frequency synthesizer for phase-noise improvement”, in Proc. European Microwave Intergrated Circuits Conference, Sept. 2006, pp.183-186.
[7]S. E. Meninger and M. H. Perrott ,”A 1-MHz Bandwidth 3.6-GHz 0.18-μm CMOS Fractional-N Synthesizer Utilizing Hybrid PFD/DAC Structure for Reduced Broadband Phase Noise,” IEEE J. Solid-State Circuit, vol.41, pp. 966-980, April 2006.
[8]S. E. Meninger and M. H. Perrott ,” A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise,” IEEE Trans. Circuits Sust. II , Analog Digit Signal Process., vol. 50, pp.839-849, Nov. 2003
[9]Sudhakar Pamarti, and Ian Galton, “A Wideband 2.4-GHz Delta-Sigma Fractional-N PLL with 1-Mb/s In-Loop Modulation,” IEEE J. Solid-State Circuits, vol. 39, pp. 49-62, Jan. 2004.
[10]S. Pamarti and I. Galton, “Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, pp.829-838, Nov. 2003.
[11]T. Bourdi, A. Borjak, and I. Kale, “A delta-sigma frequency synthesizer with enhanced phase noise performance,” in Proc. 19th IEEE Instrum. and Meas. Technology Conf., 2002, pp. 247-251.
[12]E. Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo, “A700 kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization technique for WCDMA applications,” IEEE J. Solid-State Circuits, vol. 39, pp. 1446–1454, Sep. 2004.
[13]M. Gupta and B.-S. Song, “A 1.8GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration,”IEEE J. Solid-State Circuits, vol.41, pp.2842-2851, Dec. 2006.
[14]H. Wang, G. Shou, and N. Wu, “An adaptive frequency synthesizer architecture reducing reference sidebands,” in Proc. IEEE International Symposium on Circuits and Systems ,2006, pp.3381-3384.
[15]C-Y Kuo，J-Y chang S-I Liu， “A Spur-Reduction Technique for a 5-GHz Frequency Synthesizer ’’IEEE Transcation on Circuits and Systems--I:RegularPapers ,vol.53,Mar 2006
[16]V. Kratyuk, P. K. Hanumolu, U-K Moon, K. Mayaram, “A low spur fractional-N frequency synthesizer architecture,” in Proc. IEEE International Symposium on Circuits and Systems ,2005, pp.2807-2810.
[17]彭康峻，無線通訊分數式頻率合成器之現場可程式邏輯陣列電路設計，國立中山大學電機工程研究所碩士論文, 2000.
[18]B. Miller and R. J. Conley, “A multiple modulator fractional divider,” IEEE Trans. Instrumentation and Measurement, pp. 578-583, June 1991.
[19]W. Rhee, B. S. Song, and A. Ali, “A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order Delta-Sigma modulator,” IEEE J. Solid-State Circuits, pp. 1453-1460, Oct. 2000.
[20]T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta-sigma modulation in fractional frequency synthesis,” IEEE J. Solid-State Circuits, vol. 28, pp. 553-559, May 1993.
[21]P. Kiss, J. Arias, D. Li, and V. Boccuzzi, “Stable high-order delta-sigma digital-to-analog converters,” IEEE Trans. Circuits and Systems I: Regular Papers, vol. 51, pp. 200-205, Jan. 2004.
[22]M. Bram De and M. S. J. Steyaert, “On the analysis of Delta-Sigma fractional-N frequency synthesizers for high-spectral purity, ” IEEE Trans.Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, pp. 784-793, Nov. 2003.
[23]M. H. Perrott, M. D. Trott, and C. G. Sodini, “A modeling approach for Sigma-Delta fractional-N frequency synthesizers allowing straightforward noise analysis,” IEEE J. Solid-State Circuits, vol. 37, pp. 1028-1038, Aug. 2002.
[24]D.Butterfield and B.Sun, “Prediction of Fractional-N Spurs for UHF PLL Frequency Synthesizers”, IEEE MTT-S Symposium on Technologies for Wireless Applications, pp.29-34, 1999.
[25]Delta-Sigma Modulator PLLs With Dithered Divide-Ratio, Agilent Technologies Inc. [Online].Available: http://www.agilent.com.
[26]PLL Design—Analysis of a Sigma-Delta Modulator Using RF Behavioral and System Simulation, Agilent Technologies Inc. [Online].Available: http://www.agilent.com.
[27]羅正斌，頻率合成器之分數式架構非線性效應研究與混合訊號IC實現，國立中山大學電機工程研究所碩士論文, 2006。
[28]T. Kamoto, N. Adachi, and K. Yamashita, “High-speed multi-modulus prescaler IC,” in 14th IEEE Int. Conf. Universal Personal Communications Dig., 1995, pp.325-328.
[29]C. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang, “A family of low-power truly modular programmable dividers in standard 0.35-um CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, pp.1039-1045, July 2000.
[30]H. Zarie, O. Shoaei, and S. M. Fakhraie, “A 37-mW fully integrated GMSK modulator for DRRS standard in 0.6-mm digital CMOS process,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, pp.513-520, July 2002.
[31]Y. Akazawa, H. Kikuchi, A. Iwata, T. Matsuura, and T. Takahashi, “Low power 1 GHz frequency synthesizer LSI’s,” IEEE J. Solid-State Circuits, vol. SC-18, pp.115-121, Feb. 1983.
[32]N. Cong, J. M. Andrews, D. M. Boulin, S. C. Fang, S. J. Hillenius, and J. A. Michejda, “Multigigahertz CMOS dual-modulus prescaler IC,” IEEE J. Solid-State Circuits, vol. 23, pp.1189-1194, Oct. 1988.
[33]Patrik Larsson, “High-speed architecture for a programmable frequency divider and a dual-modulus prescaler,” IEEE J. Solid-State Circuits, vol. 31, pp.744-748, May 1996.
[34]W. Rhee, B. S. Song, and A. Ali, “A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator,” IEEE J. Solid-State Circuits, vol. 35, pp.1453-1460, Oct. 2000.
[35]S. H. Yang, C. H. Lee, and K. R. Cho, “A CMOS dual-modulus prescaler based on a new charge sharing free D-flip-flop,” in 14th Annu. IEEE Int. Conf. ASIC/SOC Dig., 2001, pp.276-280.
[36]B. Chi and B. Shi, “An optimized structure CMOS dual-modulus prescaler using dynamic circuit technique,” in Proc. IEEE of Int. Conf. Computers, Communications, Control and Power Engineering, pp.1089-1092,2002.
[37]W. R. Yang, J. L. Lao, F. Ran, and J. Wang, “A 2.5 GHz CMOS dual-modulus prescaler for RF frequency synthesizer,” in Proc. 7th Int. Conf. Solid-State and Integrated Circuits Technology Dig., 2004, pp.1547-1550.
[38]J. Craninckx and Michiel S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divided-by-128/129 prescaler in 0.7-um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp.890-897, July 1996.
[39]A. Benachour, S. H. K. Embabi, and A. Ali, “A 1.5GHz, sub-2mW CMOS dual-modulus prescaler,” in 1999 IEEE Proc. Custom Integrated Circuits, pp.613-616.
[40]N. Krishnapura and P. R. Kinget, “A 5.3-GHz programmable divider for HiPerLAN in 0.25-um CMOS,” IEEE J. Solid-State Circuits, vol. 35, pp.1019-1024, July 2000.
[41]K. Shu, E. S. Sinencio, and J. S. Martinez, “A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling,” in Proc. IEEE International Symposium on Circuits and Systems, pp.791-794,2002.
[42]K. Shu and E. S. Sinencio, “A 5-GHz prescaler using improved phase switching,” in Proc. IEEE International Symposium on Circuits and Systems, pp.85-88,2002.
[43]K. Shu, E. S. Sinencio, J. S. Martinez, and S. H. K. Embabi, “A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier,” IEEE J. Solid-State Circuits, vol. 38, pp.866-874, June 2003.
[44]X. P. Yu, M. A. Do, J. G. Ma, K. S. Yeo, R. Wu and G. Q. Yan, “Low power high-speed CMOS dual modulus prescaler design with imbalanced phase-switching technique,” in Proc. IEE Conf. Circuits, Devices and Systems Dig., 2005, pp.127-132.
[45]V. Fan, “Model, analyze, and simulate ΣΔ fractional-N frequency synthesizers – part 1,” Microwave and RF, pp.183-194, Dec. 2000.
[46]V. Fan, “Model, analyze, and simulate ΣΔ fractional-N frequency synthesizers – part 2,” Microwave and RF, pp.150-154, Jan. 2001.
[47]Y. Akazawa, H. Kikuchi, A. Iwata, T. Matsuura, and T. Takahashi, “Low power 1 GHz frequency synthesizer LSI’s,” IEEE J. Solid-State Circuits, vol. SC-18, pp.115-121, Feb. 1983.
[48]N. Cong, J. M. Andrews, D. M. Boulin, S. C. Fang, S. J. Hillenius, and J. A. Michejda, “Multigigahertz CMOS dual-modulus prescaler IC,” IEEE J. Solid-State Circuits, vol. 23, pp.1189-1194, Oct. 1988.
[49]Patrik Larsson, “High-speed architecture for a programmable frequency divider and a dual-modulus prescaler,” IEEE J. Solid-State Circuits, vol. 31, pp.744-748, May 1996.
[50]W. Rhee, B. S. Song, and A. Ali, “A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator,” IEEE J. Solid-State Circuits, vol. 35, pp.1453-1460, Oct. 2000.
[51]S. H. Yang, C. H. Lee, and K. R. Cho, “A CMOS dual-modulus prescaler based on a new charge sharing free D-flip-flop,” in 14th Annu. IEEE Int. Conf. ASIC/SOC Dig., 2001, pp.276-280.
[52]W. R. Yang, J. L. Lao, F. Ran, and J. Wang, “A 2.5 GHz CMOS dual-modulus prescaler for RF frequency synthesizer,” in Proc. 7th Int. Conf. Solid-State and Integrated Circuits Technology Dig., 2004, pp.1547-1550.
[53]M. H. Perrott, “Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizer,” Ph.D. dissertation, Dept. Elecrical Eng. Comp.Science.MIT,Cambridge, MA, 1997.
[54]M. A. Do, X. P. Yu, J. G. Ma, K. S. Yeo, R. Wu and Q. X. Zhang, “GHz programmable counter with low power consumption,” Electron. Lett., vol. 39, pp.1572-1573, Oct. 2003.
[55]M. A. Do, X. P. Yu, J. G. Ma, K. S. Yeo, R. Wu and Q. X. Zhang, “GHz programmable counter with low power consumption,” in IEEE Int. Conf. Electron Devices and Slid-State Circuits Dig., 2003, pp.269-272.
[56]H. H. Chang and J. C. Wu, “A 723-MHz 17.2-mW CMOS programmable counter,” IEEE J. Solid-State Circuits, vol. 33, pp.1572-1575, Oct. 1998.
[57]S. H. Lee and H. J. Park, “A CMOS high-speed wide-range programmable counter,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, pp.638-642, Sep. 2002.
[58]N. H. E.Weste and K. Eshraghian, Principles of CMOS VLSI Design—A Systems Perspective, 2nd ed. ,MA: Addison-Wesley, 1992.
[59]D. Theil, C. Durdodt, A. Hanke, S. Heinen, S. van Waasen, D. Seippel, D. Pham-Stabner, and K. Schumacher,“A fully integrated CMOS frequency synthesizer for Bluetooth,” in IEEE RFIC Conf. Dig., 2001, pp. 103-106.
[60]C. Lam and B. Razavi, “A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4um CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 788-794, May 2000.
[61]W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” in Proc. IEEE Int. Conf. Circuits and Systems, 1999, pp. 545-548.
[62]M. El-Hage and Y. Fei, “Architectures and design considerations of CMOS charge pumps for phase-locked loops,” in Proc. IEEE Canadian Conference on Electrical and Computer Engineering, 2003, pp. 223-226.
[63]H. Chih-Ming and K. K. O, “A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop,“ IEEE J. Solid-State Circuits, pp. 521-525, Apr. 2002.
[64]A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, pp. 717-724, May 1999.
[65]W. HongMo, A. Hajimiri, and T. H. Lee, ”Comments on ”Design issues in CMOS differential LC oscillators”[and reply],” IEEE J. Solid-State Circuits, pp. 286-287, Feb. 2000.
[66]J. Lin, M. Jian-Guo, Y. Kiat Seng, and D. Manh Anh, “9.3-10.4-GHz-band cross-coupled complementary oscillator with low phase-noise performance,” IEEE Trans. Microwave Theory and Techniques, pp. 1273-1278, April 2004.
[67]“Design considerations for using the PE323x/PE333x in fractional-N or sigma-delta designs,” Application Note 12, Peregrine Semiconductor, 2001.
[68] Integer-N PD PLL Loop Filter Calculator, Peregrine Semiconductor Co.[on line].Available: http://www.peregrine-semi.com