半導體元件不斷在微縮，除了面臨傳統矽材料的物理極限外，更面臨到熱積存容忍值越來越低，摻雜物形狀難以控制到理想狀態，導致元件性能衰退，為了解決此問題，我們提出利用金屬與半導體接面取代傳統PN接面，利用不同功函數金屬形成蕭特基或歐姆接觸，使金屬與半導體接面產生類摻雜的特性，進而形成不同種類的元件。
本篇論文分為兩部分，第一部分以模擬為主，主要以矽材料當通道，模擬矽背閘極場效電晶體，調變源汲極接觸型態，形成不同型態元件，藉由電子電洞濃度圖與能帶圖，分析元件與元件導通機制。其中我們提出一邊使用歐姆接觸一邊使用蕭特基接觸，形成一個閘極控制的PIN電晶體架構，並且搭配上汲極偏壓，形成閘極控制的PIN穿隧電晶體。此元件根據模擬結果，在汲極電壓為0.35 V，源極使用蕭特基接觸(ØB = 0.1 eV)、汲極使用歐姆接觸，可以得到開關電流比(ION/IOFF ratio)為2.56×10^9，導通電流為3.63×10^(-7)A，最小次臨界百幅為7.25 mv/dec，平均次臨界擺幅為12.7 mv/dec，展現高開關電流比與低次臨界擺幅優異性能。
根據第一部分原理分析後的基礎，第二部分我們以實驗為主，以CVD的方式沉積二硫化钼當通道材料，並選擇鈦與二硫化钼形成歐姆接觸，金與二硫化钼形成蕭特基接觸，利用掀離式金屬製程，完成二硫化钼背閘極場效電晶體。根據電性量測結果，通道材料為兩層二硫化钼，汲極偏壓為7 V，汲極採用金金屬，源極採用鈦金屬，構成二硫化钼背閘極NIP Lubistor場效電晶體，可獲得開啟關閉電流比為9.72×10^3，最小次臨界擺福1280 mv/dec，平均次臨界擺福為2980 mv/dec，元件導通機制為傳統熱離子放射。接著汲極偏壓為7V，汲極採用鈦金屬，源極採用金金屬，構成二硫化钼背閘極PIN穿隧場效電晶體，元件導通機制為源極蕭特基位障穿隧，可獲得開啟關閉電流比3.27×10^3，最小次臨界擺福817 mv/dec，平均次臨界擺福為3150 mv/dec，並且可獲得更低的關閉電流。
最後分析多層二硫化钼在大氣下的可靠度，發現使用我們這種方法所沉積出來的二硫化钼經過一個月過後，門檻電壓略為往正方向偏移，開關電流比幾乎沒退化持續維持約104，整體電性上並沒有發現明顯的衰退，在大氣中表現高穩定性，未來有極大的潛力取代現今矽通道材料。
本篇論文所提出利用金半接面取代傳統PN接面的新穎概念，解決熱預算過高的問題與減少製程成本。我們利用此新穎概念製作出低次臨界擺幅、高開關電流比的穿隧場效電晶體，將來可以應用在IOT、物聯網、低功號領域，可供半導體產業進行更深入的開發與研究。

Semiconductor device are constantly scaling. In addition to facing the physical limits of silicon materials, they are also facing higher and higher thermal budget. It is difficult to control the doping profile, resulting in degradation of device performance. In order to solve this problem, we propose The metal-semiconductor junction is used to replace the traditional P-N junction, and the different metals work function metals are used to form Schottky or ohmic contacts, so that the metal-semiconductor junction has similar doping characteristics, thereby forming different types of device.
In the chapter.We first discuss the simulation of Si Back-Gated FET. It mainly uses silicon as the channel materail to simulate silicon Si Back-Gated FET. The Source and Drain contact types are modulated to form different types of components. Hole and Electron concentration chart and energy band diagram to analyze the device operation mechanism . Among them, we proposed to use ohmic contacts and Schottky contacts to form a Gate-controlled PIN transistor structure, and with the drain bias to form a gate-controlled PIN Schottky tunneling transistor. According to the simulation results, when the drain voltage is 0.35 V, the Source used Schottky contact (ØB = 1.0 eV), and the Drain used ohmic contact, the ION/IOFF ratio can reach 2.56×10^9. The ION current was 3.63×10^(-7)A, the SSmin is 7.25 mv/dec, and the SSavg is 12.7 mv/dec, showing excellent performance with high ION/IOFF ratio and low SSavg .
Based on the basic analysis of the first part of operation mechanism, in the second part we focus on experiments, depositing MoS2 as the channel material by CVD, and choosing Ti to form ohmic contact with MoS2, and Au and MoS2 to form Schottky Contact, using lift-off process to complete the MoS2 Back-Gated FET. According to the electrical measurement results, the channel material is bilayer MoS2, VD is 7 V, the Drain is made of Au, and the Source is made of Ti, which forms the MoS2 Back-Gated NIP FET. ION/IOFF ratio achieved9.72×10^3, the SSmin is 1280 mv/dec, and the SSavg is 2980 mv/dec. The transport mechanism is traditional thermionic emission. Then VD is 7 V, the Drain is made of Ti, and the Source is made of Au to form a MoS2 Back-Gated PIN TFET. The transport mechanism is Source Schottky barrier Tunneling. ION/IOFF ratio reached 3.27×10^3, the SSmin is 817 mv/dec, and the SSavg is 3150 mv/dec. and the lower IOFF current.
Finally, we analyzed the reliability of the multilayer MoS2 in the atmosphere, and found that the threshold voltage of the MoS2 was slightly shifted in the positive direction after a month, and the ION/IOFF ratio remained almost about 104., There is no obvious decline in performance, and it exhibits high stability in the atmosphere, and has great potential to replace current Si materials in the future.
The novel concept of using the M-S junction to replace the traditional P-N junction proposed in this paper can solve the problem of excessive thermal budget and reduce the process cost, We use this novel concept to fabricate TFET with low SSavg and high ION/IOFF ratio, which can be applied in the fields of IOT, and low power in the future. This new concept can be used for more in-depth development and research in the semiconductor industry.

目錄
中文審定書 i
致謝 ii
摘要 iii
目錄 viii
圖次 x
表次 xv
第一章 介紹 1
1.1研究背景 1
1.2動機 4
第二章 物理機制與實驗參數萃取方式 6
2.1金屬半導體接面 6
2.2 二維材料蕭特基接觸電流傳導機制 7
2.3熱離子放射機制 9
2.4穿隧機制 10
2.5門檻電壓萃取 10
2.6次臨界擺幅萃取 11
第三章 傳統矽材料元件模擬與設計 13
3.1模擬軟體相關機制與物理模型 13
3.2矽背閘極控制電阻 (JLFET) 15
3.3矽背閘極控制PNP (PMOSFET) 18
3.4矽背極控制NIP (Lubistor FET ) 21
3.5矽背閘極控制PIN (TFET) 25
3.6矽背閘極場效電晶體元件比較 31
第四章 二硫化钼背閘極場效電晶體設計與製程 33
4.1 元件架構設計 33
4.2製程步驟 33
4.3閘及氧化層成長與破片 34
4.4二硫化钼介紹 36
4.5二硫化钼沉積方式 38
4.6二硫化钼沉積 39
4.7掀離式金屬製程 40
4.8黃光參數 41
4.9金屬蒸鍍參數 43
4.10不同源汲極金屬二硫化钼背閘極電晶體製作 45
第五章 實驗結果與討論 48
5.1相同源汲極金屬二硫化钼背閘極場效電晶體的電性分析 48
5.2二硫化钼層數比較 55
5.3不同源汲極金屬二硫化钼背閘極控制NIP分析(Lubistor FET) 57
5.4不同源汲極金屬二硫化钼背閘極控制PIN分析 (TFET) 59
5.5二硫化钼在大氣中可靠度 62
5.6二硫化钼背閘極場效電晶體比較 65
第六章 結論與未來展望 67
6.1結論 67
6.2未來展望 68
參考文獻 70

 

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