隨著現代的科技日新月異，今日世界中晶片的需求日漸增加，1960年代，第一顆電晶體在貝爾實驗室問世。幾年之後，英特爾的共同創辦人 Gorden Moore 提出了摩爾定律，意為:在IC上一樣大的面積，電晶體的數量會每過兩年就成長一倍。隨著製程節點微縮，雖然性能上會有所提升，例如:開態電流變大、元件封裝密度提高。但也會伴隨一些問題產生，最主要一項即為閘極漏電。傳統的金氧半場效電晶體（MOSFET）微縮到極小尺寸時會遇到物理厚度限制及閘極(Gate)漏電過大的問題。因此，在1999年胡正明博士發明了鰭式場效電晶體（FinFET）。不僅解決了漏電問題，更延續摩爾定律的生命。本研究主要探討FinFET在不同製程變因下的電性和可靠度分析，進而提出物理機制。
在本文中的第四章中，會探討兩種不同氣體含氮量退火製程的元件在電性上的差異，發現含氮量較多的元件相對於較少的會有較大臨界電壓(Vt)、較差的次臨界擺幅(S.S.)、較小的轉導(gm)，以及較低的開態驅動電流(Ion)，從而得知製程的氣體含氮量會影響元件氧化層和通道介面的品質，進而比較通道介面之缺陷數，使用Charge Pumping(ICP)量測手法做驗證，結果得知氮對介面確實造成影響產生更多之缺陷。
本文第五章中，主要探討對兩種不同製程條件樣本進行負偏壓應力劣化(Negative Bias Stress，NBS)分析，經過此一系列的劣化實驗，比較兩者之間劣化量的差異，且使用不同通道長度的元件去做電性劣化比較，發現此元件存在氧化層邊緣效應(Oxide Edge Effect)，針對因此原因而產生的電性異常現象提出物理模型解釋。
於本文第六章中，使用與前章節一樣的兩樣本進行熱載子應力劣化(Hot Carrier Stress，HCS)與負偏壓溫度不穩定性(Negative Bias Temperature Instability，NBTI)之分析，且分別對短、中、長通道長度元件進行劣化分析，於實驗結果中驗證不同製程變因下電晶體通道也會產生邊緣效應。由此章之結論整合前章之討論，提出經過氮退火製程的FinFET元件在經過應力劣化後之完整物理模型機制。

In today's rapidly advancing world of technology, the demand for microchips is constantly increasing. In the 1960s, the first transistor was born at Bell Labs. A few years later, Intel co-founder Gordon Moore proposed Moore's Law, which states that the number of transistors on an integrated circuit (IC) of the same size would double every two years. As process nodes shrink, there are performance improvements such as increased drain current and higher component packaging density. However, this progress also gives rise to certain challenges, with one of the most significant being gate leakage. When traditional Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are scaled down to very small sizes, issues like physical thickness limitations and excessive gate leakage become prominent.
Therefore, in 1999, Dr. Hu Chen-Ming invented the FinFET (Fin Field-Effect Transistor), which not only resolved the leakage problem but also extended the life of Moore's Law. This study primarily explores the electrical characteristics and reliability of FinFETs under different process variations, and subsequently proposes the underlying physical mechanisms.
In the fourth chapter of this paper, two different nitrogen-containing annealing processes are examined to understand the differences in electrical properties of the devices. It is found that devices with higher nitrogen content exhibit higher threshold voltage (Vt), lower subthreshold swing (S.S.), lower transconductance (gm), and lower on-state drive current (Ion) compared to those with less nitrogen content. This suggests that the nitrogen content in the annealing treatment affects the quality of the oxide layer and channel interface. To further analyze the defect density in the channel interface, the Charge Pumping (ICP) measurement method is used for validation, and the results confirm that nitrogen indeed has an impact and generating more defects.
In the fifth chapter of this paper, a Negative Bias Stress (NBS) analysis is conducted on samples from two different process conditions. Through a series of degradation experiments, differences in degradation between the two conditions are compared. Additionally, devices with different channel lengths are used to compare electrical degradation. It is observed that these devices exhibit an Oxide Edge Effect, leading to anomalous electrical behavior. A physical model is proposed to explain these anomalies resulting from the oxide edge effect.
In the sixth chapter, an analysis of Hot Carrier Stress (HCS) and Negative Bias Temperature Instability (NBTI) is conducted on two different samples, using short, medium, and long channel length devices. Experimental results validate that transistor channels exhibit edge effects under different process variations. The conclusions from this chapter integrate the discussions from the previous chapters, presenting a comprehensive physical model mechanism for FinFET devices subjected to stress degradation.

論文審定書 i
論文公開授權書 ii
致謝 iii
摘要 v
Abstract vii
目錄 x
圖目錄 xii
表目錄 xv
第 一 章 緒論 1
1.1 前言 1
第 二 章 簡介與文獻回顧 4
2.1 高介電常數(High-k)材料特性 4
2.2 元件氮化(Nitridation)之影響 8
2.3 元件結構與製程 11
2.4 鰭式場效電晶體操作原理 12
第 三 章 半導體參數之萃取與分析儀介紹 15
3.1半導體參數萃取介紹 15
3.1.1 臨界電壓(Threshold Voltage，Vt) 16
3.1.2 載子遷移率(Carrier Mobility，μ) 16
3.1.3次臨界擺幅(Subthreshold Swing，S.S.) 17
3.2 半導體參數分析儀介紹 18
第 四 章 鰭式場效電晶體經氮退火處理後之濃度效應分析 20
4.1 簡介 20
4.2 實驗架構 21
4.3 實驗結果與討論 22
第 五 章 在氮退火處理期間產生之氧化層邊緣效應分析 29
5.1 簡介 29
5.2 實驗架構 30
5.3 實驗結果與討論 30
第 六 章 在氮退火處理期間產生之通道邊緣效應分析 40
6.1 簡介 40
6.2 實驗架構 41
6.3 實驗結果與討論 43
第 七 章 結論 54
參考文獻 55

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