本論文研究題目配合科技部計畫「複合式矽光子陀螺儀晶片與微型化模組開發(IV) — 子計畫四: 訊號處理晶片研製」，為使訊整合訊號處理晶片整體的精確度及線性度提升，本論文針對時間差異放大器(Time-Difference Amplifier, TDA) 及數位類比轉換器(Digital to Analog Converter, DAC) 進行研究探討。
時間差異放大器常用於鎖相迴路(PLL) 和時間數位轉換器(Time to Digital Converter, TDC) 中，使其解析度能有效提升。本論文提出一具可調整輸入時間差及可變增益之自動重置電流式時間差異放大器，具有極寬之輸入時間差、可變增益及低的增益誤差，並另外設置重置功能，使其能進行下一筆時間放大運算。本設計佈局後線性輸入時間差範圍為± 13730 ps，時間放大增益範圍為2.4 - 57.8，增益誤差可小於4%，量測結果則因未妥善考慮負載效應對內部電路的影響，所以未量測到預期之時間放大結果。
本論文考量到FOG 系統晶片對外在製程敏感的特性，提出另個具自我校正功能之雙模式選取12-bit 100 MS/s 電流驅動式數位類比轉換器(DAC)，此DAC 可對製程飄移進行偵測及增加自我校正(Self-Calibration) 功能，以提升其線性度。晶片佈局後之模擬結果為，在奈奎斯特頻率之下SFDR 為77.5 dB，DNL 為0.09，INL為0.95。

This thesis is partially supported by MOST project“Heterogeneous Silicon Photonics Gyroscope Chip and Miniaturized Module Development (IV) — Sub-project 4: The Implementation of Signal Processing Chips”. To improve the overall accuracy and linearity of the signal processing chip, this thesis is focused on the Time-Difference Amplifier (TDA) and Digital-to-Analog Converter (DAC) in the mentioned system.
TDA is often used in Phase-locked loop (PLL) and Time to Digital Converters (TDC) to enhance the resolution. In this thesis, an auto-reset current type TDA with adjustable input time difference and variable gain is proposed, which has wide input time difference, variable gain, and low gain error, and an additional reset function enabling the next time difference amplification operation. The linear input time-difference range is ± 13730 ps, and the time amplification gain range is 2.4 - 57.8 with a gain error of less than 4%. However, due to lack of loading effect considerations in the layout process, the measurement outcome does not meet the expected performance.
Considering the sensitive feature of the FOG system chip to the process variation, a dual-mode selectable 12-bit 100 MS/s current mode DAC with self-calibration function is proposed, which detects the process variation to activate self-calibartion function so as to improve the linearity. The post-layout simulation result shows that SFDR is 77.5 dB, DNL is 0.95, and INL is 0.09.

論文審定書. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
論文摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
圖目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
表目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
1 概論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 前言. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 相關文獻與技術探討. . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 TDA 功能說明. . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.2 TDA 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.3 DAC 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 研究動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 論文大綱. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 具可調整增益之電流式時間差異
放大器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 TDA 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 具可調整增益之電流式TDA 系統架構. . . . . . . . . . . . . . . . . 15
2.2.1 整體系統電路運作. . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 具可調增益之電流式TDA 之各子電路設計. . . . . . . . . . . . . . . 16
2.3.1 輸入訊號偵測及延遲電路. . . . . . . . . . . . . . . . . . . . 16
2.3.2 時間差異放大器核心電路. . . . . . . . . . . . . . . . . . . . 18
2.3.3 增益編碼器. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.4 電流源控制開關電路. . . . . . . . . . . . . . . . . . . . . . . 23
2.3.5 施密特比較器. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.6 重置電路. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.7 電流源控制開關電路之功能數值表. . . . . . . . . . . . . . . 28
2.4 時間差異放大器參數推導. . . . . . . . . . . . . . . . . . . . . . . . . 29
2.4.1 線性輸入時間差最大值(Maximum Linear Input Time Difference，
ΔTINMAX) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.4.2 輸入訊號頻率最大值(Maximum Input Signal Frequency，FMAX) 29
2.5 電路模擬結果和預計規格. . . . . . . . . . . . . . . . . . . . . . . . . 30
2.5.1 IN1 領先IN2 之模擬結果. . . . . . . . . . . . . . . . . . . . . 31
2.5.2 IN2 領先IN1 之模擬結果. . . . . . . . . . . . . . . . . . . . . 32
2.5.3 時間放大增益模擬結果表. . . . . . . . . . . . . . . . . . . . 34
2.5.4 預計規格比較表. . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.6 晶片照相圖. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.6.1 量測環境. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.6.2 量測結果與原因探討. . . . . . . . . . . . . . . . . . . . . . . 38
2.7 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3 具自我校正功能之雙模式選取12-bit
100 MS/s 電流驅動式數位類比轉換器. . . . . . . . . . . . . . . . . . . . . 42
3.1 DAC 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2 具自我校正功能之雙模式選取12-bit 100 MS/s 電流驅動式DAC 系
統電路架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.3 本論文之DAC 之各子電路設計. . . . . . . . . . . . . . . . . . . . . 44
3.3.1 製程偵測及編碼電路. . . . . . . . . . . . . . . . . . . . . . . 44
3.3.2 電流源陣列. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.3 開關栓鎖電路. . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.4 雙模式編碼器. . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.5 補償電路. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.4 模擬結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4.1 雙模式編碼電路模擬. . . . . . . . . . . . . . . . . . . . . . . 51
3.4.2 數位類比轉換器動態參數模擬. . . . . . . . . . . . . . . . . . 52
3.4.3 預計規格表. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.4.4 有無補償功能之比較表. . . . . . . . . . . . . . . . . . . . . . 54
3.5 結果與討論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4 結論及未來研究方向. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.1 研究結論和研究成果. . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2 未來研究方向. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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