垂直互連結構雖具有較短的物理長度以及較佳的電性特性，但其對應之接地腳排列方式卻會嚴重影響其特性阻抗，使得訊號在傳遞的過程中容易產生阻抗不匹配，而造成訊號的反射。因此，本論文致力於垂直互連結構的寬頻可擴展物理模型的建立，主要方法是利用多影像線電荷法分析垂直互連結構訊號腳與接地腳間的基板寄生電容。本論文所提出的物理模型，可有效預測垂直互連結構在不同的接地腳排列下之特性阻抗，以提供阻抗匹配最佳化設計方法。本論文分別討論矽穿孔及彈簧針兩種不同垂直互連結構。在矽穿孔部分，本論文提出用於單端與差動訊號傳輸之物理模型，並利用此模型來分析當間距對直徑比值改變時，對特性阻抗值的影響；在彈簧探針部分，當以單端訊號傳輸時，分別在四種對稱型接地結構排列下，比較其對特性阻抗值的影響。在實驗部分，為了改善利用傳統式共平面探針平台進行垂直互連量測時，往往需要繁複的去嵌化技術將測試治具的效應校正掉，以得到垂直互連之真實高頻響應，然而其有效校正頻寬仍受到限制。因此，在本研究開發雙面探針工作站以及零延遲穿透校正技術，在量測垂直互連結構時可避免複雜的去嵌化程序，故能更直接、精準、快速的獲得垂直互連結構的電性特性。相較於傳統的量測方法，其量測頻寬可以大幅提升。最終，本論文分別進行矽穿孔及彈簧針之模型預測、電磁模擬及量測等散射參數結果之比較，都具有良好的吻合度，因此可有效驗證本論文所提出針對垂直互連結構之物理模型化方法。

Despite the shorter physical length and superior electrical properties of the vertical interconnects, the arrangement of corresponding grounding pins drastically affects the characteristic impedance, resulting in impedance mismatch during the propagation of signals, which leads to signal reflection. Therefore, to potentially overcome this disadvantage, this dissertation endeavors to establish the physical model of the vertical interconnects for improving the impedance-matching design. The key approach is to use the method of multiple image-line charges for analyzing the substrate parasitic capacitance between the signal pin and grounding pins of the vertical interconnect. The proposed physical models are capable of predicting accurately the changes in characteristic impedance of various grounding pin arrangements in the vertical interconnect, and based on the prediction results the optimal impedance-matching design can be found. In this dissertation, two types of vertical interconnects, through-silicon via (TSV) and pogo pin, are compared for discussion. Two physical models, one for single-ended signaling and the other for differential signaling, are developed to analyze how changes in TSV pitch-to-diameter ratio affect the characteristic impedance. Moreover, the same physical models are utilized to predict the changes in characteristic impedance caused by the alteration in the substrate parasitic capacitance between signal pin and grounding pins, under the circumstance that the information through the pogo pins is transmitted by single-ended signals with four different types of symmetric grounding architecture. The experiment in this work aims to improve the traditional coplanar probe stations used for measuring vertical interconnects. Traditionally, to extract the frequency response of the vertical interconnects under test, complex de-embedding techniques are required to calibrate out the parasitic effects of the test vehicle. However, the effective calibration bandwidth is limited. In response to this disadvantage, this work develops a double-sided probe station and calibrates the station with the help of a zero-delay thru. This setup can avoid the complex de-embedding process to measure the high frequency electrical properties of vertical interconnects in a more direct, accurate, and rapid manner. Compared to traditional means, the proposed method significantly enhances the measurement bandwidth. Finally, comparisons of S-parameters among the modeled, EM-simulated and measured results for the TSV and pogo pin structures are obtained. The comparisons demonstrate very good agreement, thereby verifying the proposed physical modeling methods for the vertical interconnects.

1 Introduction 1
1.1 Research Motivation 1
1.2 Through-Silicon Vias 2
1.2.1 Single-ended type 2
1.2.2 Differential type 4
1.3 Pogo Pins 4
1.4 Double-Sided Probing System 6
1.5 Dissertation Overview 7
2 Modeling of Through-Silicon Vias 8
2.1 Single-Ended Through-Silicon Vias 8
2.1.1 Physical Scalable Model 8
2.1.2 Measurement Setup and Calibration 15
2.1.3 Results and Discussion 18
2.2 Differential Through-Silicon Vias 24
2.2.1 Physical Scalable Model 24
2.2.2 Validation and Discussion 30
2.3 Summary 32
3 Modeling of Pogo Pins 33
3.1 Theoretical Approach 33
3.1.1 1S2G Configuration 37
3.1.2 1S4G Configuration 39
3.1.3 1S8G Configuration 41
3.1.4 Verification and Discussion 43
3.1.5 Physical Scalable Model 48
3.2 Measurement Setup 50
3.2.1 Double-Sided Probing System 50
3.2.2 De-embedding of Electrode Sheets 51
3.3 Results and Discussion 53
3.4 Summary 54

4 Conclusions 59
Bibliography 61
Vita 70

[1] P. Garrou, “Future ICs Go Vertical,” Semiconductor International, February 2005.
[2] Proc. of the 2nd Conference on 3D Architectures for Semiconductor Integration and Packaging, Tempe, AZ, 2005.
[3] S. F. Al-sarawi, D. Abbott, and P. D. Franzon, “A review of 3-D packaging technology,” IEEE Trans. Compon. Packag. Manuf. Technol. B, vol. 21, no. 1, pp. 2-14, Feb. 1998.
[4] K. Takahashi, Y. Taguchi, M. Tomisaka, H. Yonemura, M. Hoshino, M. Ueno, Y. Egawa, Y. Nemoto, Y. Yamaji, H. Terao, M. Umemoto, K. Kameyama, A. Suzuki, Y. Okayama, T. Yonezawa, and K. Kondo, “Process integration of 3D chip stack with vertical interconnection,” in Proc. 54th Electron. Comp. Tech. Conf., 2004, pp. 601-609
[5] C. A. Bower, D. Malta, D. Temple, J. E. Robinson, P. R. Coffman, M. R. Skokan and T. B. Welch, “High density vertical interconnects for 3-D integration of silicon integrated circuits, “in Proc. 56th Electron. Comp. Tech. Conf., 2006, pp. 399-403
[6] K. Bernstein, P. Andry, J. Cann, P. Emma, D. Greenberg, W. Haensch, M. Ignatowski, S. Koester, J. Magerlein, R. Puri, and A. Young, “Interconnects in the third dimension: design challenges for 3D ICs, “in Proc. 44th Ann. Design Automation Conf., 2007, pp. 562-567.
[7] J. H. Lau, Reliability of RoHS Compliant 2D & 3D Electronic Interconnects, McGraw-Hill, 2010.
[8] H. -H. S. Lee and K. Chakrabarty, “Test challenges for 3D integrated circuits, “ IEEE Des. Test Comput., pp. 26-35.Oct. 2009.
[9] P. D. Franzon, W. R. Davis, M. B. Steer, S. lipa, E. C. Oh, T. Thorolfsson, S. Melamed, S. Luniya, T. Doxsee, S. Berkeley, B. Shani, and K. Obermiller, “Design and CAD for 3D integrated circuits, ” “in Proc. 45th Ann. Design Automation Conf., 2008, pp. 668-673.
[10] D. H. Kim, K. Athikulwongse, and S. K. Lim, “A study of through-silicon-via impact on the 3D stacked IC layout,” in Proc. Int. Conf. on Computer-Aided Design, 2009, pp. 674-680.
[11] J. H. Lau, “TSV manufacturing yield and hidden costs for 3D IC integration, ” in Proc. 60th Electron. Comp. Tech. Conf., 2010, pp. 1031-1042.
[12] Q. Chen and J. Zhao, “Via and return path discontinuity impact on high speed digital signal quality,” in IEEE Elect. Performance of Electron. Packag. Conf., Oct. 2000, pp. 215-218.
[13] E. R. Pillai, “Coax via—a technique to reduce crosstalk and enhance impedance match at vias in high-frequency multilayer,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 10, pp. 1981-1985, Oct. 1997.
[14] G. Antonini, A. C. Scogna, and A. Orlandi, “Equivalent network synthesis for via holes discontinuities,” IEEE Trans. Adv. Packag., vol. 25, no. 4, pp. 528-536, Nov. 2002.
[15] R. S. Patti, “Three-dimensional integrated circuits and the future of system-on-chip designs,” Proc. IEEE, vol. 94, pp. 1214-1224, Jun. 2006.
[16] M. Hubner and J. becker, Multiprocessor System-on-Chip. New York, NY: , Springer, 2009.
[17] M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low power methodology manual: for system on chip design. New York, NY: Springer, 2007.
[18] W. Wolf, A. A. Jerraya, and G. Martin, “Multiprocessor system-on-chip (MPSoC) technology,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. vol. 27, no. 10, pp. 1701-1713, Oct. 2008.
[19] K. M. Brown, “System in package "the rebirth of SIP",” in Proc. IEEE Custom Integrated Circuits Conf., 2004, pp. 681-686.
[20] F. Roozeboom, A. L. A. M. Kemmeren, J. F. C. Verhoeven, F. C. van den Heuvel, J. Klootwijk, H. Kretschman, T. Fric, E. C. E. van Grunsven, S. Bardy, C. Bunel, D. Chevrie, F. LeCornec, S. Ledain, F. Murray, and P. Philippe, “Passive and heterogeneous integration towards a Si-based System-in-Package concept, ” Thin Solid Films, vol. 504, May 2006, pp. 391-396.
[21] J. Miettinen, V. Pekkanen, K. Kaija, P. Mansikkamaki, J. Mantysalo, M. Mantysalo, J. Niittynen, J. Pekkanen, T. Saviauk, and R. Ronkka, “Inkjet printed System-in-Package design and manufacturing,” J. Mircoelectronics, Apr. 2008, pp. 1740-1750.
[22] D. H. Kim, S. Mukhopadhyay, and S. K. Lim, “Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs,” in Proc. ACM/IEEE Int. Workshop on System Level Interconnect Prediction, July 2009, pp. 85–92
[23] T. Thorolfsson, K. Gonsalves, and P. D. Franzon, “Design automation for a 3DIC FFT processor for synthetic aperture radar: A case study,” in Proc. ACM Design Automation Conf., July 2009, pp. 51–56.
[24] D. H. Kim, K. Athikulwongse, and S. K. Lim, “A study of through-silicon-via impact on the 3D stacked IC layout,” in Proc. IEEE Int. Conf. on Computer-Aided Design, Nov. 2009, pp. 674–680.
[25] Yole Crop.[Online]. Available: http://www.semicontaiwan.org/en/sites/
semicontaiwan.org/files/docs/4._mkt__jerome__yole.pdf
[26] E.-X. Liu, E.-P. Li, W.-B. Ewe, H. M. Lee, T. G. Lim, and S. Gao, “Compact wideband equivalent-circuit model for electrical modeling of through-silicon via,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 6, pp. 1454-1460, Jun. 2011.
[27] J. Kim, J. S. Pak, J. Cho, E. Song, J. Cho, H. Kim, T. Song, J. Lee, H. Lee, K. Park, S. Yang, M. -S. Suh, K. -Y. Byun, and J. Kim, “High-frequency scalable electrical model and analysis of a through silicon via (TSV),” IEEE Trans. Comp., Packag., Manuf. Technol., vol. 1, no. 2, pp. 181-195, Feb. 2011.
[28] T.-Y. Cheng, C.-D. Wang, Y.-P. Chiou, and T.-L, Wu, “A new model for through-silicon vias on 3-D IC using conformal mapping method,” IEEE Microw. Wireless Compon. Lett., vol. 22, no. 6, pp. 303-305, Jun. 2012.
[29] J. S. Pak, J. Cho, J. Kim, J. Lee, H. Lee, K. Park, and J. Kim, “Slow wave and dielectric quasi-TEM modes of metal-insulator-semiconductor (MIS) structure through silicon via (TSV) in signal propagation and power delivery in 3D chip package,” in Proc. 60th Electron. Comp. Tech. Conf., 2010, pp. 667-672.
[30] K. Yoon, G. Kim, W. Lee, T. Song, J. Lee, H. Lee K. Park, and J. Kim, “Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer,” in IEEE 11th Electron. Packag. Tech. Conf., Feb. 2009, pp. 702-706.
[31] L. Yu, H. Yang, T. T. Jing, M. Xu, R. Geer, and W. Wang, “Electrical characterization of RF TSV for 3D multi-core and heterogeneous ICs,” in Proc. Int. Conf. Computer-Aided Design, 2010, pp. 686-693.
[32] C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, and J. Kim, “High frequency electrical model of through wafer via for 3-D stacked chip packaging,” in Electron. Systemintegration Tech. Conf., Sept. 2006, pp. 215-220.
[33] D. M. Jang, C. Ryu, K. Y. Lee, B. H. Cho, J. Kim, T. S. Oh, W. J. Lee, and J. Yu, “Development and evaluation of 3-D SiP with vertically interconnected through silicon vias (TSV),” in Proc. 57th Electron. Comp. Tech. Conf., 2007, pp. 847-852.
[34] R. Wang, G. Charles, and P. Franzon, “Modeling and Compare of Through-Silicon-Via (TSV) in High Frequency,” in IEEE Int. 3D Systems Integration Conf., Feb. 2012, pp. 1-6.
[35] K. Salah, H. Ragai Y. Ismail, and A.E. Rouby, “Equivalent lumped element models for various n-port through silicon vias networks,” 16th Asia and South Pacific Design Automation Conf., Jan. 2011, pp. 176-183.
[36] Y. P. R. Lamy, K. B. Jinesh, F. Roozeboom, D. J. Gravvesteijn, and W. F. A. Besling, “RF characterization and analytical modelling of through silicon vias and coplanar waveguides for 3D integration,” IEEE Trans. Adv. Packag., vol. 33, no. 4, pp. 1072-1079, Nov. 2010.
[37] T. G. Lim, Y. M. Khoo, C. S. Selvanayagam, D. S. W. Ho, R. Li, X. Zhang, G. Shan, and X. Y. Zhong, “Through silicon via interposer for millimetre wave applications,” in Proc. 61st Electron. Comp. Tech. Conf., 2011, pp. 577- 582.
[38] H. Kim, J. Cho, M. Kim, K. Kim, J. Lee, H. Lee, K. Park, K. Choi, H.-C. Bae, J. Kim, and J. Kim, “Measurement and analysis of a high-speed TSV channel, ” IEEE Trans. Comp., Packag., Manuf. Technol., vol. 2, no. 10, pp. 1672-1685, Oct. 2012.
[39] C. -W. Luo, Y. -C. Wu, J. -Y. Wang,and S. S.H. Hsu, “RF modeling of through silicon vias (TSVs) in 3D IC, “ Int. Conf. Solid State Devices and Materials, 2010, pp. 239-240.
[40] D. M. Jang, C. Ryu, K. Y. Lee, B. H. Cho, J. Kim, T. S. Oh, W. J. Lee, and J. Yu, “Development and evaluation of 3-D SiP with vertically interconnected through silicon vias (TSV) , “ in Proc. 57th Electron. Comp. Tech. Conf., 2007, pp. 847- 852.
[41] C. Fuchs, J. Charbonnier, S. Cheramy, L. Cadix, D. Henry, P. Chausse, O. Hajji, A. Farcy, G. Garnier, C. Brunet-Manquat, J. Diaz, R. Anciant, P. Vincent, N. Sillon, and P. Ancey, “Process and RF modelling of TSV last approach for 3D RF interposer,” in Proc. IEEE Int. Interconnect Tech. Conf. & Mat. for Adv. Metal., 2011.
[42] L. Fourneaud, T. Lacrevaz, J. Charbonnier, C. Fuchs, A. Farcy, C. Bermond, E. Eid, J. Roullard, and B.Flechet,“Extraction of equivalent high frequency models for TSV and RDL interconnects embedded in stacks of the 3D integration technology,” IEEE Workshop on Signal Propagation on Interconnects, pp. 61-64, May 2011.
[43] K.-C. Lu, T.-S. Horng, H.-H. Li, K.-C. Fan, T.-Y Huang, and C.-H. Lin, “Scalable modeling and wideband measurement techniques for a signal TSV surrounded by multiple ground TSVs for RF/high-speed applications,” in Proc. 62nd Electron. Comp. Tech. Conf., 2012, pp. 1023-1026.
[44] K.-C. Lu and T.-S. Horng, “Comparative modeling study of single-ended through-silicon via between the G-S and G-S-G configuration,” in IEEE Int. Microw. Symp. Dig., 2013, pp. TH2G-3:1-3.
[45] J. Kim, J. S. Park, J. Cho, J. Lee, H. Lee, K. Park, and J. Kim, “Modeling and analysis of differential signal through silicon via (TSV) in 3D IC,” in Proc. IEEE Comp., Packag., Manuf. Technol. Symp., 2010, pp. 24-26.
[46] N. Langston. Optimizing contactors for high-performance test sockets. [Online]. Available: http://electroiq.com/blog/2004/03/optimizing-contactors-for-high-
performance-test-sockets/
[47] Winway Technology Co., Ltd. Field application guide of winway test socket. [Online] Available: http://www.winwayglobal.com/CHSC/PhotoData/Field_
Application_Guide_of_WinWay_20130408_1.pdf
[48] B. B. Szendrenyi, H. Barnes, J. Moreira, and M. Wollitzer, “Addressing the broadband crosstalk challenges of pogo pin type interfaces for high-density high-speed digital applications,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2007, pp. 2209-2212.
[49] J. Moreira and H. Verkmann. An engineer's guide to automated testing of high-speed interfaces. Artech House, MA: 2010, ch. 8.
[50] S. -M. Wu and S. -W. Guan, “A novel signal integrity methodology by 3D direct analysis for microwave testing probes,” Progress In Electromagnetics Research C, vol. 15 ,2010.
[51] J. Moreira, H. Barnes, W. Burns, D. Sionne, C. Gutierrez and F. Azeem, “Influence of dielectric materials on ATE test fixtures for high-speed digital applications," in Proc. 6th Int. Kharkov Conf. on the Physics and Engineering of Microwave, Millimeter and Submillimeter Waves , June 2007, pp. 806-809.
[52] Agilent Application Note. Basics of Measuring the Dielectric Properties of Materials. PN 5989-2589EN. [Online]. Available: http://www3.imperial.ac.uk/
pls/portallive/docs/1/11949698.PDF
[53] J. Moreira, H. Barnes, H. Kaga, M. Comai, B. Roth and M. Culver, "Beyond 10 gbps challenges of characterizing future I/O interfaces with automated test equipment," IEEE Int. Test Conf., Oct. 2008, pp. 1-10.
[54] R. B. Sun, R. B. Wu and S. W. Hsiao, "Compromised impedance match design for signal integrity of pogo pins structures with different signal-ground patterns," IEEE Signal Propagation on Interconnects, 2009, pp. 1-4.
[55] R. B. Sun, C. Y. Wen, Y. C. Chang and R. B. Wu, “A new isolation structure of pogo pins for crosstalk reduction in a test socket," IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, pp. 586-594, Apr. 2011.
[56] M.-K. Chen, C.-C. Tai, Y. J. Huang, and L.-K. Fang, “Electrical characterization of BGA test socket for high-speed applications,” Proc. 4th Int. Symp. on Electronic Materials and Packag., Dec. 2002, pp123-126.
[57] H. Barnes, J. Moreira, H. Ossoinig, M. Wollitzer, T. Schmid, and M. Tsai, “Development of a pogo pin assembly and via design for multi-gigabit interfaces on Automated Test Equipment,” in Proc. Asia-Pacific Microwave Conf., Dec. 2006, pp. 381-384.
[58] H. Barnes, J. Moreira, M. Cormai, A. Islas, F. Tamayo-Broes, M. Resso, A. Ciccomancini, O. Bell, and M. Tsai, “Performance at the DUT: Techniques for evaluating the performance of an ATE system at the device under test socket,” presented at the IEC DesignCon, San Diego, CA, Feb. 4-7, 2008.
[59] J. Kelly and M. Engelhardt, Advanced Production Testing of RF, SoC, and SiP Devices. Norwood, MA: Artech House, chs. 1, 9, 11.
[60] Winway Technology Co., Ltd. [Online]. Available: http://www.winwayglobal.
com/home01.aspx?ID=1
[61] W. Humann, “Compensation of transmission line loss for Gbit/s test on ATEs,” in Proc. IEEE Int. Test Conf., Oct. 2002, pp. 430-437.
[62] H. Barnes, J. Moreira, T. McCarthy, W. Burns, C. Gutierrez, and M. Resso. ATE Interconnect Performance to 43Gbps Using Advanced PCB Materials. [Online] Available: http://www.taconic-add.com/pdf/technica-larticles--fastrise_ate_
digital_pcb_materials.pdf
[63] H. Barnes, and J. Moreira. Apr. 2008. ATE signal integrity challenges for multi-gigabit communication interfaces. [Online]. Available: http://www.
siliconaid.com/2008_SWDFT_presentations/SWDFT_Workshop Rev1p1_Heidi.pdf
[64] W. -D. Guo, J.-H. Lin, C.-M. Lin, T.-W. Huang, and R.-B. Wu, “Fast methodology for determining eye diagram characteristics of lossy transmission Lines,” IEEE Tran. on Adv. Packag., vol.32, no. 1, pp.175-183, Feb. 2009.
[65] W. -D. Guo, F.-N. Tsai, G.-H. Shiue, and R.-B. Wu, ”Reflection enhanced compensation of lossy traces for best eye-diagram improvement using high-impedance mismatch” IEEE Tran. on Adv. Packag., vol.31, no. 3, pp.619-626, Feb. 2008.
[66] M. W. Newman, S. Muthukumar, M. Schuelein, T. Dambrauskas, P. A. Dunaway, J. M. Jordan, S. Kulkarni, C. D. Linde, T. A. Opheim, R. A. Stingel, W. Worwag, L. A. Topic, and J. M. Swan, “Fabrication and electrical characterization of 3D vertical interconnects,” in Proc. 56th Electron. Comp. Tech. Conf., 2006, pp. 394-398.
[67] R. Cardu, M. Scandiuzzo, S. Cani, L. Perugini, E. Franchi, R. Canegallo, and R. Guerrieri, “Chip-to-chip communication based on capacitive coupling,” in Proc. IEEE Int. Conf. on 3D System Integration, 2009, pp. 1-6.
[68] H.-C. Lu, G.-M. Wu, C. Pan and Y.-T. Chou, “Coupling coefficient improvement for inductor coupled vertical interconnect in 3D IC die stacking,” in Proc. Proc. 59th Electron. Comp. Tech. Conf., 2009, pp. 1207-1212.
[69] K. Kang, J. Byun, J.-W. Jang, and H.-Y. Lee, “Signal integrity and reliability of a new multi-stack package using a pressure conductive rubber,” in Electrical Design of Adv. Packag. and Systems Symp. Dig., 2008, pp. 214-217.
[70] C.-L. Wang and R.-B. Wu, “Modeling and design for electrical performance of wideband flip-chip transition,” IEEE Trans. Adv. Packag., vol. 26, no. 4, pp. 385-391, Nov. 2003.
[71] L.-H. Hsu, W.-C. Wu, E. Y. Chang, H. Zirath, Y.-C. Wu, and C.-T. Wang, and S.-P. Tsai, “Fabrication process and 110 GHz measurement result of MS-to-CPW RF-via transition for RF-MEMS devices packaging applications,” in Proc. Int. Conf. on Compound Semiconductor Manuf. Technol., 2009, pp. 1-3.
[72] T. S. Tarter and N. T. Do, “Method and apparatus for electrical characterization of an integrated circuit package using a vertical probe station,” U.S. Patent 6396296, May 2002.
[73] T. Burcham, P. McCann, and R. Jones, “Double-sided probing structures,” U.S. Patent Application 20060043962, Mar. 2006.
[74] T. Burcham, P. McCann, and R. Jones, “Double-sided probing structures,” U.S. Patent Application 20080265925, Oct. 30, 2008.
[75] J. Krupka, J. Breeze, A. Centeno, N. Alford, T. Clausen, and L. Jensen, “Measurements of permittivity, dielectric loss tangent, and resistivity of float-zone silicon at microwave frequencies,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 11, pp. 3995-4001, Nov. 2006.
[76] S. A. Wartenberg,“Selected topics in RF coplanar probing, ” IEEE Trans. Microw. Theory Tech., vol. 51, no. 4, pp. 1413-1421, Apr. 2003.
[77] K.-C. Lu, Y.-C. Lin, T.-S. Horng, S.-M. Wu, C.-C. Wang, C.-T. Chiu, and C.-P. Hung, “Vertical interconnect measurement techniques based on double-sided probing system and short-open-load-reciprocal calibration,” in Proc. 61th Electron. Comp. Tech. Conf., 2011, pp. 2130- 2133.
[78] A. Fenero and U. Pisani, “Two-port network analyzer calibration using an unknown thru,” IEEE Microw. Guided Wave Lett., vol. 2, no. 12, Dec. 1992.
[79] S. Basu and L. Hayden, “An SOLR calibration for accurate measurement of orthogonal on-wafer DUTs,” in IEEE Int. Microw. Symp. Dig., 1997, pp. 1335-1338.
[80] K.-C. Lu, T.-S. Horng, C.-H. Chen, C.-Y. Hung, P.-N. Lee, M.-J. Wang, C.-P. Hung, and H.-M. Tong, “Scalable modeling of through silicon vias up to millimeter-wave frequency,” in Proc. IEEE Electrical Design of Advanced Package & Systems Symp., 2012, pp. 170-173.
[81] K. Y. Mong, C. E. Kee, L. T. Guan, L. Enxiao,” High Frequency Characterization of Through Silicon Via Structure,” in IEEE Electron. Packag. Tech. Conf., pp.536-540, Feb. 2010.
[82] S. W. Ho, S. W. Yoon, Q. Zhou, Pasad K., Kripesh V., Lau, J. H.,” High RF performance TSV silicon carrier for high frequency application,” in Proc. 58th Electron. Comp. Tech. Conf., June 2008, pp.1946-4952.
[83] Cadix, L., Rousseau, M., Fuchs, C., Leduc, P., Thuaire, A., El Farhane, R., Chaabouni, H., Anciant, R., Huguenin, J.-L., Coudrain, P., Farcy, A., Bermond, C., Sillon, N., Flechet, B., Ancey, P.,” Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs,” in IEEE Interconnect Techn. Conf., July 2010, pp.1-3.
[84] Eid, E., Lacrevaz, T., Bermond, C., de Rivaz, S., Capraro, S., Roullard, J., Cadix, L., Fléchet, B., Farcy, A., Ancey, P., Calmon, F., Valorge, O., Leduc, P.,” Characterization and modeling of RF substrate coupling effects due to vertical interconnects in 3D integrated circuit stacking,” in IEEE Signal Propagation on Interconnects, June 2010, pp.35-38.