晶圓背面研磨(Back Grinding)是半導體產業常用到的製程技術之一，能夠用來減少晶片的厚度，清除汙染物，增加散熱率，並且表面光滑有利於後續製程的進行，因此判斷研磨的好壞相當重要。
本研究探討的項目分為兩個部分，第一個是測量薄型矽晶圓的表面粗糙度，首先基於田口設計法選出七種晶圓研磨參數，再利用粗糙度表面輪廓機沿著晶圓表面，由內而外依序測量，並且選用中心線平均粗度(Ra)當作量測基準，可以發現表面粗糙度的數值內小外大排列，顯示越是外圍的晶圓，其表面受到的破壞程度越大；接著搭配理論計算砂輪與晶圓的研磨參數值，觀察在不同晶圓自轉速、砂輪自轉速、砂輪進給率的參數下，對於晶圓表面應力的施加，同時使用有限元素軟體ANSYS 18.2用以模擬動態晶圓研磨的應力變化；最後將實驗、理論與模擬的結果相互對照，實現運用有限元素模擬的方式預測晶圓研磨表面粗糙度的數值。
第二個研究項目探討扇出型封裝的製程中，研磨晶片和環氧樹脂的表面應力變化，這是因為在研磨後晶圓會因為殘餘應力的釋放產生翹曲現象，故本研究利用動態模擬晶圓研磨的技術，來驗證扇出型晶圓的實際翹曲量，並且預測在不同晶片排列底下的翹曲量數值。最後利用實驗設計的中央合成法決定出七種晶圓的影響因子進行模擬，並利用迴歸直線分析找出最佳化參數，經研究改善晶圓翹曲幅度可達25%，故可有效降低晶圓翹曲之數值。

Back grinding is one of the most commonly used manufacturing process techniques in the semiconductor industry. It can reduce the thickness of silicon wafer, clean and remove stains, increase the heat dissipation rate, and also improve the surface lubricity during subsequent manufacturing process. Therefore, it is important to judge back grinding quality in the silicon wafer.
The items to be explored in this research are divided into two parts, the surface roughness of a thin silicon wafer is first measured, the number of seven types of silicon wafer polishing selected by the Taguchi design, the roughness of the silicon wafer surface along the surface grinding line measure by surfcorder. From internal to external measurement, center line with arithmetic mean deviation (Ra) for measurement standard, surface roughness number inside small outside large arrangement, appearance over the outside wafer edge, the degree of destroy on the surface. Furthermore, theoretical calculation of wheel and wafer grinding process parameter, observed surface stress under different wafer rotation speed, wheel rotation speed and wheel feed rate. Used finite element software ANSYS 18.2 simulated dynamic silicon wafer grinding stress change. Finally, comparison of experiment, theory and simulation results. Predictive silicon wafer grinding surface roughness values.
The second research about Fan-Out wafer-level packaging (FOWLP), grinding both silicon chip and epoxy molding compound (EMC) observe surface stress distribution. After grinding the phenomenon of warpage due to the residual stress released. Used dynamic simulated silicon wafer grinding technology to verify FOWLP actually warpage, and predict different chip arrangement FOWLP warpage values. Eventually, dealing with the central composite design from the experimental design, and then determine seven influence factors to simulate. Using linear regression analysis to find out the parameters optimization, it can improve the wafer warpage up to 25% and reduce the values.

論文審定書 i
誌謝 ii
摘要 iii
Abstract iv
目錄 vi
圖目錄 ix
表目錄 xiii
中英文對照表 xv
第一章緒論 1
1.1前言 1
1.2研究背景 3
1.3研究動機 12
1.4研究目的 13
1.5論文結構 14
第二章文獻回顧 15
2.1前言 15
2.2研磨實驗 16
2.3研磨模擬 21
2.4表面粗糙度量測相關文獻 23
2.5裂紋深度與損傷層之研究 27
2.6 Fan in/out結構失效之研究 32
2.7 Fan-Out晶片翹曲相關之研究 34
2.8 RDL重分佈層相關之研究 35
2.9 EMC材料相關之研究 38
2.10結語 41
2.11文獻回顧之整理 42
第三章矽晶圓研磨研究 52
3.1前言 52
3.2矽晶圓實驗流程圖 54
3.3實驗樣品 55
3.4實驗方法 57
3.5實驗量測位置 67
3.6實驗結果 68
3.7矽晶圓研磨理論 73
3.7.1研磨顆粒的滑動力與切削力 78
3.7.2砂輪研磨晶圓的總研磨力 80
3.7.3表面粗糙度之理論計算 81
3.7.4理論計算之材料參數 83
3.7.5次表面之裂紋深度 86
3.8矽晶圓研磨模擬 88
3.8.1一次因子參數影響 91
3.8.2矽晶圓研磨應力之模擬分析探討 96
3.9結語 101
第四章Fan-Out晶圓翹曲研究 102
4.1前言 102
4.2 Fan-Out晶圓翹曲之研究 103
4.3 Fan-Out晶圓研磨厚度 104
4.4 Fan-Out晶片邊界條件設定 106
4.5 Fan-Out晶片建模尺寸 108
4.6 Fan-Out材料參數 109
4.7 Fan-Out晶圓翹曲量驗證 111
4.8不同Fan-Out晶片排列之結構 114
4.9不同Fan-Out晶片排列之切割道變化 118
4.10結語 120
第五章實驗設計之結果與討論 121
5.1前言 121
5.2流程圖 122
5.3實驗因子 123
5.4 ANOVA分析 124
5.5中央合成設計 127
5.6迴歸分析 128
5.7影響因子占比 132
5.8反應曲面設計 133
5.9迴歸方程式 146
5.10結論 149
第六章結論與未來展望 152
6.1結論 152
6.2未來展望 153
參考文獻 154
附件一 169
附件二 176

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