由於矽(Silicon, Si)元件在摩爾定律(Moore’s Law)已接近極限，高遷移率鍺(Germanium, Ge)擁有比Si更高的載子遷移率被視為有前途的材料，不過矽與鍺的晶格常數不匹配約4%，會導致矽上磊晶鍺後，矽鍺之接面處錯位差排(Mixed Dislocation)產生將會影響元件性能。在本次研究實現鍺基通道低溫層轉移利鍵合技術，將較佳磊晶品質的鍺基通道層轉移至氧化層上(Germanium On Insulator, GeOI)，可以擁有與絕緣體上矽(Silicon On Insulator, SOI)相同優點，降低基板漏電流，並且僅使用300℃退火即可提高鍵結強度，降低元件熱預算。
本論文研究設計中，基於層轉移技術鍺基通道製作之鰭式場效電晶體(FinFET)，設計不同通道寬度與閘極長度製成之p-FET與n-FET比較，發現p-FET在通道寬度20奈米時即可達S.S.=91mV/dec並且ION/IOFF=達到106電流開關比；n-FET在通道50奈米時也可達S.S.=89mV/dec並且ION/IOFF=達到106電流開關比，不過由於鍺與金屬接觸有強烈費米能階釘札(Fermi-Level Pinning, FLP)的現象在價帶(Valence Band)附近，導致元件性能被限制無法有效調變。接著同時也研究了鍺矽接面錯位差排對於元件影響，發現GeOI元件在p-FET可以更好抑制短通道效應(Short Channel Effects, SCEs)；在n-FET可以提供更好的導通電流。

Due to the nearing limits of Moore's Law for silicon devices, high-mobility germanium is considered a promising material with higher carrier mobility than Si. However, the mismatch in lattice constants between silicon and germanium, approximately 4%, leads to the generation of mixed dislocations at the silicon-germanium interface when germanium is epitaxially grown on silicon. This mixed dislocation can have implications on the performance of devices utilizing the silicon-germanium interface. In this study, we achieved low-temperature layer transfer of a germanium-based channel using a bonding technique. By transferring the Ge-based channel layer with improved epitaxial quality onto an oxide layer (Germanium On Insulator), we can obtain similar advantages to silicon (Silicon On Insulator) on an insulator substrate. This approach reduces substrate leakage current and requires only a 300-degree annealing process to enhance bonding strength, thereby reducing the device’s thermal budget.
In this research study, we designed germanium-based fin field-effect transistors (FinFETs) using layer transfer techniques. We compared p-FET and n-FET devices with different channel widths and gate lengths. We found that p-FET devices achieved a subthreshold swing of 91mV/dec and an ION/IOFF ratio of 106 in 20-nanometer channel width. n-FET devices, on the other hand, achieved a subthreshold swing of 89mV/dec and an ION/IOFF ratio of 106 in a 50-nanometer channel width. However, due to the phenomenon of Fermi-Level Pinning at the valence band, strong Fermi-level pinning at the interface between germanium and the metal contact. This limitation hinders device performance modulation.
Furthermore, the impact of germanium-silicon interface dislocations on device performance was also investigated. It was found that Ge On Insulator devices exhibited better suppression of short channel effects in p-FET channels while providing improved conductivity in n-FET devices.

論文審定書i
誌謝ii
摘要iv
Abstractv
目錄vii
圖目錄ix
表目錄xii
第一章 緒論1
1.1研究動機1
1.2短通道效應(Short Channel Effects, SCEs)2
1.3高遷移率鍺通道材料3
1.4鰭式場效電晶體(FinFET) 與全環閘極場效電晶體(Gate-All-Around FET, GAAFET)6
1.5基板漏電流7
1.6費米能階釘札(Fermi-Level Pinning, FLP)8
1.7低溫異質鍵合技術9
第二章 元件製作11
2.1 低溫異質鍵合技術11
2.1.1晶圓準備11
2.1.2 低溫異質鍵合技術製作流程13
2.1.3 鍵合晶圓回蝕刻製程14
2.2GeOI FinFET元件製作流程17
2.2.1 主動區形成19
2.2.2 高介電常數金屬閘極(High-k Metal Gate, HKMG)20
2.2.3 離子佈值摻雜21
2.2.4 接觸與金屬化21
2.3材料分析22
2.3.1 High-K 介電層材料選擇22
2.3.2 X射線繞射分析 (X-ray Diffraction, XRD)27
2.3.3 穿透式電子顯微鏡(Transmission electron microscope, TEM)29
第三章 結果與討論30
3.1 不同通道寬度(Wch)與通道長度(LG)之 ID-VG特性30
3.1.1 GeOI p-FET與n-FET之ID-VG曲線31
3.1.2 GeOI p-FET於VDS = -0.05V之ID-VG34
3.1.3 GeOI n-FET 於VDS= -0.05V之ID-VG38
3.1.4 結論42
3.2 GeSOI FinFET與GeOI FinFET特性比較43
3.2.1 結論47
3.3 GeOI FinFET電壓傳輸特性(VTC)曲線48
第四章 結論與未來展望49
4.1 全環繞閘極結構49
4.2 鍺超薄通道(Ultra Thin Body, UTB)50
參考文獻52

[1] F. Schwierz and J. J. Liou, "Status and Future Prospects of CMOS Scaling and Moore's Law - A Personal Perspective," 2020 IEEE Latin America Electron Devices Conference (LAEDC), San Jose, Costa Rica, 2020, pp. 1-4, doi: 10.1109/LAEDC49063.2020.9073539.
[2] C. -T. Chung et al., "Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High ION/IOFF Ratio Ge FinFETs," in IEEE Transactions on Electron Devices, vol. 60, no. 6, pp. 1878-1883, June 2013, doi: 10.1109/TED.2013.2259173.
[3] P. Zheng, Y. -B. Liao, N. Damrongplasit, M. -H. Chiang and T. -J. K. Liu, "Variation-Aware Comparative Study of 10-nm GAA Versus FinFET 6-T SRAM Performance and Yield," in IEEE Transactions on Electron Devices, vol. 61, no. 12, pp. 3949-3954, Dec. 2014, doi: 10.1109/TED.2014.2360351.
[4] X. Yu, J. Kang, M. Takenaka and S. Takagi, "Evaluation of Mobility Degradation Factors and Performance Improvement of Ultrathin-Body Germanium-on-Insulator MOSFETs by GOI Thinning Using Plasma Oxidation," in IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1418-1425, April 2017, doi: 10.1109/TED.2017.2662217.
[5] A. Toriumi and T. Nishimura, "Germanium CMOS potential from material and process perspectives: Be more positive about germanium," Jpn. J. Appl. Phys., vol. 57, no. 1, p. 010101, Jan. 2018, doi: 10.7567/JJAP.57.010101.
[6] P. Goley and M. Hudait, "Germanium Based Field-Effect Transistors: Challenges and Opportunities," Materials, vol. 7, no. 3, pp. 2301–2339, Mar. 2014, doi: 10.3390/ma7032301.
[7] H. Wong and K. Kakushima, "On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node," Nanomaterials, vol. 12, no. 10, p. 1739, May 2022, doi: 10.3390/nano12101739.
[8] V. B. Sreenivasulu and V. Narendar, "Design Insights of Nanosheet FET and CMOS Circuit Applications at 5-nm Technology Node," in IEEE Transactions on Electron Devices, vol. 69, no. 8, pp. 4115-4122, Aug. 2022, doi: 10.1109/TED.2022.3181575.
[9] A. K. Gundu and V. Kursun, "5-nm Gate-All-Around Transistor Technology With 3-D Stacked Nanosheets," in IEEE Transactions on Electron Devices, vol. 69, no. 3, pp. 922-929, March 2022, doi: 10.1109/TED.2022.3143774.
[10] J.-H. Lee, “Comparison of SOI FinFETs and Bulk FinFETs,” ECS Meeting Abstracts, vol. MA2009-01, no. 23, p. 941, May 2009, doi: 10.1149/MA2009-01/23/941.
[11] M. J. H. van Dal et al., "Ge n-channel FinFET with optimized gate stack and contacts," 2014 IEEE International Electron Devices Meeting, San Francisco, CA, USA, 2014, pp. 9.5.1-9.5.4, doi: 10.1109/IEDM.2014.7047018.
[12] M. H. Lee, S. T. Chang, S. Maikap, C. . -Y. Peng and C. . -H. Lee, "High Ge Content of SiGe Channel pMOSFETs on Si (110) Surfaces," in IEEE Electron Device Letters, vol. 31, no. 2, pp. 141-143, Feb. 2010, doi: 10.1109/LED.2009.2036138.
[13] P. Kumari and V. R. Rao, "Fermi-Level Depinning in Germanium Using Black Phosphorus as an Interfacial Layer," in IEEE Electron Device Letters, vol. 40, no. 10, pp. 1678-1681, Oct. 2019, doi: 10.1109/LED.2019.2935402.
[14] X. Luo, T. Nishimura, T. Yajima and A. Toriumi, "Potential Influence of Surface Atomic Disorder on Fermi-level Pinning at Metal/SiGe Interface," 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), Kobe, Japan, 2018, pp. 47-49, doi: 10.1109/EDTM.2018.8421410.
[15] M. Caymax et al., "Germanium for advanced CMOS anno 2009: a SWOT analysis," 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore, MD, USA, 2009, pp. 1-4, doi: 10.1109/IEDM.2009.5424320.
[16] K. J. Kuhn, "Considerations for Ultimate CMOS Scaling," IEEE Trans. Electron Devices, vol. 59, no. 7, pp. 1813–1828, Jul. 2012, doi: 10.1109/TED.2012.2193129.
[17] S. Chaurasia, S. Raghavan and S. Avasthi, "Epitaxial germanium thin films on silicon (100) using two-step process," 2016 3rd International Conference on Emerging Electronics (ICEE), Mumbai, India, 2016, pp. 1-4, doi: 10.1109/ICEmElec.2016.8074631.
[18] J. Mitard et al., "First demonstration of 15nm-WFIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe Source/Drain," 2014 IEEE International Electron Devices Meeting, San Francisco, CA, USA, 2014, pp. 16.5.1-16.5.4, doi: 10.1109/IEDM.2014.7047065.
[19] W. Lin et al., "Low-Temperature Oxide Wafer Bonding for 3-D Integration: Chemistry of Bulk Oxide Matters," in IEEE Transactions on Semiconductor Manufacturing, vol. 27, no. 3, pp. 426-430, Aug. 2014, doi: 10.1109/TSM.2014.2323941.
[20] S. H. Christiansen, R. Singh and U. Gosele, "Wafer Direct Bonding: From Advanced Substrate Engineering to Future Applications in Micro/Nanoelectronics," in Proceedings of the IEEE, vol. 94, no. 12, pp. 2060-2106, Dec. 2006, doi: 10.1109/JPROC.2006.886026.
[21] R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka and S. Takagi, "High-Mobility Ge pMOSFET With 1-nm EOT Al2O3/GeOx/Ge Gate Stack Fabricated by Plasma Post Oxidation," in IEEE Transactions on Electron Devices, vol. 59, no. 2, pp. 335-341, Feb. 2012, doi: 10.1109/TED.2011.2176495.
[22] D. Rathee, M. Kumar, and S. K. Arya, "CMOS development and optimization, scaling issue and replacement with high-k material for future microelectronics," Int. J. Comput. Appl, vol. 8, no. 5, p. 10, 2010, doi: 10.5120/1208-1730.
[23] H. Shang et al., "Germanium channel MOSFETs: Opportunities and challenges," in IBM Journal of Research and Development, vol. 50, no. 4.5, pp. 377-386, July 2006, doi: 10.1147/rd.504.0377.
[24] L. Liu, M. Zhao, R. Liang, J. Wang and J. Xu, "Demonstration of Germanium nMOSFETs with interface passivation of ozone pre-gate treatment and ozone ambient annealing," 2014 International Symposium on Next-Generation Electronics (ISNE), Kwei-Shan Tao-Yuan, Taiwan, 2014, pp. 1-2, doi: 10.1109/ISNE.2014.6839324.
[25] S. Takagi et al., "Gate dielectric formation and MIS interface characterization on Ge," Microelectronic Engineering, vol. 84, no. 9–10, pp. 2314–2319, Sep. 2007, doi: 10.1016/j.mee.2007.04.129.
[26] 利泓科技”拉曼光譜儀分析原理｜Raman”
https://www.rightek.com.tw/product_list/raman%E6%8B%89%E6%9B%BC%E5%85%89%E8%AD%9C%E5%84%80%E5%88%86%E6%9E%90%E5%8E%9F%E7%90%86/
[27] H. Zang, W. Y. Loh, J. D. Ye, G. Q. Lo and B. J. Cho, "Tensile-Strained Germanium CMOS Integration on Silicon," in IEEE Electron Device Letters, vol. 28, no. 12, pp. 1117-1119, Dec. 2007, doi: 10.1109/LED.2007.909836.
[28] X 光繞射 (XRD) 學院
https://www.thermofisher.com/tw/zt/home/industrial/spectroscopy-elemental-isotope-analysis/spectroscopy-elemental-isotope-analysis-learning-center/elemental-structural-analysis-information/xrd-academy.html
[29] T. . -Z. Hong et al., "First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT)," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 15.5.1-15.5.4, doi: 10.1109/IEDM13553.2020.9372001.
[30] K. Natori, "Ballistic/quasi-ballistic transport in nanoscale transistor," Applied Surface Science, vol. 254, no. 19, pp. 6194–6198, Jul. 2008, doi: 10.1016/j.apsusc.2008.02.150.
[31] Y. Sun, Y. Gu, B. Chen, X. Yu and R. Cheng, "A Ballistic Transport Study for Advanced Transistors in Post-Moore Era: Parasitic Resistance, Self-heating and Cryogenic Analysis," 2021 International Conference on IC Design and Technology (ICICDT), Dresden, Germany, 2021, pp. 1-4, doi: 10.1109/ICICDT51558.2021.9626397.
[32] Bohr, M. and Mistry, K. (2011) Intel’s Revolutionary, 22 nm Transistor Technology. https://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf
[33] W. H. Chang et al., "First Experimental Observation of Channel Thickness Scaling Induced Electron Mobility Enhancement in UTB-GeOI nMOSFETs," in IEEE Transactions on Electron Devices, vol. 64, no. 11, pp. 4615-4621, Nov. 2017, doi: 10.1109/TED.2017.2756061.
[34] X. Yu, J. Kang, M. Takenaka and S. Takagi, "Evaluation of Mobility Degradation Factors and Performance Improvement of Ultrathin-Body Germanium-on-Insulator MOSFETs by GOI Thinning Using Plasma Oxidation," in IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1418-1425, April 2017, doi: 10.1109/TED.2017.2662217.
[35] Y. Huangfu, W. Zhan, X. Hong, X. Fang, G. Ding, and H. Ye, "Heteroepitaxy of Ge on Si(001) with pits and windows transferred from free-standing porous alumina mask," Nanotechnology, vol. 24, no. 18, p. 185302, Apr. 2013, doi: 10.1088/0957-4484/24/18/185302.