本論文主要分為三部份，第一部分主要是探討電晶體中之各種不同雜訊來源與其雜訊等效模型，並針對目前文獻上熱門之雜訊抵銷電路架構進行分析，並詳細推導雜訊抵銷低雜訊放大器電路架構之理論。第二部份則是實際以共閘極雜訊抵銷電路架構進行雜訊抵銷之實驗，藉由調整電晶體之轉導值，探討在不同雜訊抵銷條件下，其雜訊指數之模擬與量測結果比較。第三部份則是採用共源極電阻回授之雜訊抵銷架構，利用TSMC 0.18μm RF CMOS製程設計一個應用於DVB-H系統並成功具有雜訊抵銷功能之寬頻低雜訊放大器RFIC。

This thesis is composed of three parts. The first part is devoted to introducing the various noise sources in transistors and their equivalent noise models. Based on the equivalent noise models, the theory of noise cancellation in a low-noise amplifier is derived in detail. The second part is to perform an experiment to validate the theory of low-noise amplifier using common-gate noise cancellation technique. By adjusting the transconductance of individual transistor, the simulated and measured noise figures are compared under different noise cancellation conditions. The third part is to design a low-noise amplifier RFIC using common-source noise cancellation technique for DVB-H applications. This RFIC was implemented in a TSMC 0.18μm process and measured to show successful noise cancellation capability in a wide frequency range.

目錄 I
圖目錄 III
表目錄 VI
第一章　緒論 1
1.1 雜訊簡介 1
1.2 低雜訊放大器 3
1.2.1 雜訊匹配設計 4
1.2.2電感性源極退化設計 4
1.2.3 雜訊抵銷設計 5
1.2.4 電容交互耦合設計 6
1.3 研究動機 7
1.4 章節介紹 7
第二章　低雜訊放大器之雜訊抵銷設計方法 8
2.1 場效電晶體之雜訊模型 8
2.2 雜訊抵銷電路架構 16
2.2.1 共源極電阻回授之雜訊抵銷架構 16
2.2.2 共閘極之雜訊抵銷架構 20
2.2.3共源極與共汲極電阻回授之雜訊抵銷架構 23
2.3 共閘極雜訊抵銷電路之設計原理 24
第三章　低雜訊放大器之雜訊抵銷模擬與實驗 28
3.1 實驗架構 28
3.2 模擬流程 29
3.3 模擬與量測結果比較 32
第四章　雜訊抵銷低雜訊放大器之CMOS RFIC設計 41
4.1 電路設計 41
4.2 模擬與量測結果比較 43
4.3 規格比較 50
第五章　結論 51
參考文獻 52

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